MC13892JVLR2 Freescale, MC13892JVLR2 Datasheet - Page 47

• Manufacturer Part Number: MC13892JVLR2
• Manufacturer: Freescale

Specifications of MC13892JVLR2

• Operating Temperature (max): 85C
• Operating Temperature (min): -30C
• Mounting: Surface Mount
• Package Type: BGA
• Case Length: 12mm
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Compliant

Table 12. Interrupt, Mask and Sense Bits
INTERRUPT HANDLING
CONTROL
to the processor by driving the INT pin high. This is true whether the communication interface is configured for the SPI or I
interrupt can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register. This will also cause the interrupt line
to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high.
the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor
the option of polling for status from the IC. The IC powers up with all interrupts masked except the USB Low power boot, so the
processor must initially poll the device to determine if any interrupts are active. Alternatively, the processor can unmask the
interrupt bits of interest. If a masked interrupt bit was already high, the interrupt line will go high after unmasking.
They are read only, and not latched or clearable.
period before an interrupt is generated.
BIT SUMMARY
descriptions, refer to the related chapters.
Analog Integrated Circuit Device Data
Freescale Semiconductor
ADCDONEI
ADCBISDONEI
TSI
CHGDETI
USBOVI
CHGREVI
CHGSHORTI
CHGFAULTI
CHGCURRI
CCCVI
BPONI
LOBATLI
BVALIDI
The MC13892 has interrupt generation capability to inform the system on important events occurring. An interrupt is signaled
Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high,
The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources.
Interrupts generated by external events are debounced, meaning that the event needs to be stable throughout the debounce
Table 12
Interrupt
summarizes all interrupt, mask, and sense bits associated with INT control. For more detailed behavioral
ADCDONEM
ADCBISDONEM
TSM
CHGDETM
USBOVM
CHGREVM
CHGSHORTM
CHGFAULTM
CHGCURRM
CCCVM
BPONM
LOBATLM
BVALIDM
Mask
-
-
-
CHGDETS
CHGENS
USBOVS
-
-
CHGFAULTS[1:0]
CHGCURRS
CCCVS
BPONS
LOBATLS
BVALIDS
Sense
ADC has finished requested
conversions
ADCBIS has finished requested
conversions
Touch screen wake-up
Charger detection sense is 1 if
detected
Charger state sense is 1 if active
VBUS over-voltage
Sense is 1 if above threshold
Charger path reverse current
Charger path short circuit
Charger fault detection
00 = Cleared, no fault
01 = Charge source fault
10 = Battery fault
11 = Battery temperature
Charge current below threshold
Sense is 1 if above threshold
CCCVI transition detection
BP turn on threshold detection.
Sense is 1 if above threshold.
Low battery detect
Sense is 1 if below LOBATL
threshold
USB B-session valid
Sense is 1 if above threshold
Purpose
Trigger DebounceTi
FUNCTIONAL DEVICE OPERATION
L2H
L2H
Dual
Dual
Dual
L2H
L2H
L2H
H2L
Dual
L2H
L2H
Dual
me
0
0
30ms
32 ms
100 ms
60 μs
1.0 ms
1.0 ms
10 ms
1.0 ms
100 ms
30 ms
0
L2H: 20-
24 ms
H2L: 8-
12 ms
I2C INTERFACE
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