MC13892JVLR2 Freescale, MC13892JVLR2 Datasheet - Page 38

• Manufacturer Part Number: MC13892JVLR2
• Manufacturer: Freescale

Specifications of MC13892JVLR2

• Operating Temperature (max): 85C
• Operating Temperature (min): -30C
• Mounting: Surface Mount
• Package Type: BGA
• Case Length: 12mm
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Compliant

FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
PWRON1, 2 AND 3
is in effect a parallel path for the power key.
has the global reset feature enabled by default. The 13892B version has the global reset feature disabled by default, but can be
enabled by setting the SPI bit GLBRSTENB = 0. The global reset feature powers down the part, disables the charger, resets the
SPI registers to their default value and then powers back on. To enable a global reset the PWRON3 pin needs to be pulled low
for greater than 12 seconds and then pulled back high. If the PWRON3 pin is held low for less than 12 seconds the pin will act
as a normal PWRON pin.
PUMS1 AND PUMS2
Power Up Mode Select pins (PUMS1 and PUMS2) are used to configure the start-up characteristics of the regulators. Supply
enabling and output level options are selected by hardworking the PUMS pins for the desired configuration.
MODE
for normal operation or test mode via the MODE pin as summarized in the following table.
GNDCTRL
SPIVCC
CS
to VCORE at Cold Start configures the interface for I
CS pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin).
CLK
MOSI
addresses (A0 address selection).
MISO
GNDSPI
38
13892
A turn on event can be accomplished by connecting an open drain NMOS driver to the PWRONx pin of the 13892, so that it
In addition to the turn on event, the 13892A/B versions include a global reset feature on the PWRON3 pin. The 13892A version
Power up mode supply setting. Default start-up of the device is selectable by hardwiring the Power Up Mode Select pins. The
USB LBP mode, normal mode, test mode selection & anti-fuse bias. During evaluation and testing, the IC can be configured
Ground for control logic.
Supply for SPI bus and audio bus
CS held low at Cold Start configures the interface for SPI mode. Once activated, CS functions as the SPI Chip Select. CS tied
Because the SPI interface pins can be reconfigured for reuse as an I
Primary SPI clock input. In I
Primary SPI write input. In I
Primary SPI read output. In I
Ground for SPI interface.
2
2
C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible
2
C mode, this pin is the SCL signal (I
C mode, this pin is the SDA signal (bi-directional serial data line).
MODE PIN STATE
Ground
VCOREDIG
VCORE
2
C mode; the pin is not used in I
2
C bus clock).
MODE
2
Normal Operation
USB Low Power Boot Allowed
Test Mode
C interface, a configuration protocol mandates that the
2
C mode other than for configuration.
Analog Integrated Circuit Device Data
Freescale Semiconductor