LSI53CF92A LSI, LSI53CF92A Datasheet - Page 84

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

4-34
Register: 0x0D
Configuration 4 (Config 4)
Read/Write
Register Bank 0 or 1
The reserved bits in this register are ignored on writes. This register is
reset to zero on power-up or chip reset, but not on SCSI reset.
R
R
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
7
1
Note:
0
This register is accessible in either Register Bank 0 or 1.
Reserved
This bit is set to 1 as soon as the chip is enabled.
Reserved
These bits remain set to 0.
R
DMA Write to FIFO
DREQ is true whenever the top eight bytes of the
FIFO are empty.
DMA Read from FIFO
End of transfer
Target mode: DREQ is set when the transfer counter
is zero or ATN/ is set.
Initiator Synchronous Data In: DREQ is true when the
transfer counter is less than eight.
Initiator mode, not Synchronous Data In: DREQ is
true when the transfer counter is zero, or after any
phase change.
Not end of transfer
Initiator Synchronous Data In: DREQ is true if the
transfer counter is greater than seven and the bottom
eight bytes of the FIFO are full.
Not Initiator Synchronous Data In: DREQ is true
whenever the bottom eight bytes of the FIFO are full.
0
4
0
Default
RBS
3
0
EAN
2
0
1
1
R
0
1
[6:4]
7