LSI53CF92A LSI, LSI53CF92A Datasheet - Page 70

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LSI53CF92A

Manufacturer Part Number
LSI53CF92A
Description
Manufacturer
LSI
Datasheet

Specifications of LSI53CF92A

Lead Free Status / RoHS Status
Not Compliant

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4-20
Table 4.4
The upper three bits are reserved by LSI Logic. This register defaults to
0x55 after hardware reset or the Reset Chip command (but not SCSI
reset). Refer to the descriptions for the FASTCLK and FASTSCSI bits,
Configuration 3 (Config
operation.
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
FAST SCSI
Bit Value
Note:
0
0
0
0
0
0
0
0
0
Transfer Rate with 25 MHz Clock (FASTCLK Bit Clear)
Any combination not listed in the above tables violates
ANSI standards, and should not be used.
Register
Value
0xA
0xB
0xC
0xD
0x5
0x6
0x7
0x8
0x9
3), bits 3 and 4, for information on Fast SCSI
per Byte
Clocks
10
11
12
13
5
6
7
8
9
Transfer Rate
(Mbytes/s)
5.0
4.2
3.6
3.1
2.8
2.5
2.3
2.1
1.9

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