LSI53CF92A LSI, LSI53CF92A Datasheet - Page 31

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

2.5.4 DMA Burst Mode
The following conditions must be true for a DMA Threshold Eight transfer
to occur:
Because the Threshold Eight mode is enabled during DMA burst mode,
the DMA burst is limited to eight transfers. This feature forces the chip to
periodically relinquish control of the DMA channel, allowing other devices
to gain access to the bus to perform such operations as memory refresh.
Burst mode, or Alternate DMA mode, is a special mode devised to
maximize data throughput using most DMA controllers. DMA burst mode
is enabled by setting both the Threshold Eight and the Alternate DMA
mode bits in the
causes the FSC to delay assertion of DREQ until it can transfer eight
bytes. Alternate DMA mode causes the FSC to deassert DREQ after the
byte transfers, causing the DMA controller to relinquish the bus.
This regular surrendering of the DMA channel has benefits for two
common DMA interface problems. For DMA controllers that do not
recognize higher priority requests until the current device finishes, the
FSC can periodically force DMA arbitration. This allows DRAM refresh
and other operations to occur during SCSI operations. For DMA
controllers that are much faster than the SCSI host or peripheral to which
the system is connected, bus efficiency is improved by ensuring that the
FSC has data to transfer while the DMA controller is controlling the bus.
DMA Burst mode can be enabled in both bus configurations. DMA Burst
mode affects the deassertion of DREQ and assertion of DACK/ for DMA
reads and writes.
DMA Operation
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Threshold Eight mode is enabled.
Transfer Counter indicates eight or more bytes.
The FIFO can accommodate an 8-byte transfer as follows:
–
–
The FIFO contains at least eight bytes of data to transfer to
memory, or
At least the top eight bytes of the FIFO are empty to receive the
eight-byte transfer from memory.
Configuration 3 (Config 3)
register. Threshold Eight
2-11