LSI53CF92A LSI, LSI53CF92A Datasheet - Page 66

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

4-16
Register: 0x05
Time-Out
Write Only
Register Bank 0 or 1
Under normal operation [when the Enable Delayed Response to
Selection (ENDR) bit, bit 4 of the
cleared], this 8-bit, write only register specifies the amount of time the
FSC waits for a response during selection or reselection. (The FSC has
no way to time-out if it never wins arbitration; it keeps trying indefinitely
until it wins.) The
time-out period of 250 ms to comply with the ANSI standard.
When ENDR is set, the FSC delays its response to selection based on
the value of this register. In either case, the register value (RV) may be
calculated from:
For example, at 40 MHz, the register value that gives a 250 ms time-out
period is 153 decimal or 0x99. The clock conversion factor is defined in
the description of write address 0x09. To compute the register value
using this formula when the clock conversion factor is zero, use eight, the
number of clocks, rather than zero. The
unchanged by any reset, and the states of these bits are unpredictable
after power-up.
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
7
x
6
x
Time-Out
RV
=
5
x
------------------------------------------------------------------------------------------ -
(time-out period) (CLK frequency)
8192 clock conversion factor
register is normally loaded to specify a
4
x
Default
SCSI Control (SCONTROL)
3
x
Time-Out
2
x
register remains
1
x
register, is
0
x