74ACT715SCNL Fairchild Semiconductor, 74ACT715SCNL Datasheet - Page 8

• Manufacturer Part Number: 74ACT715SCNL
• Manufacturer: Fairchild Semiconductor

Specifications of 74ACT715SCNL

• Lead Free Status / RoHS Status: Compliant

©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
Horizontal and Vertical Gating Signals
Horizontal Drive and Vertical Drive outputs can be uti-
lized as general purpose Gating Signals. Horizontal and
Vertical Gating Signals are available for use when Com-
posite Sync and Blank signals are selected and the
value of Bit 2 of the Status Register is 0. The Vertical
Gating signal will change in the same manner as that
specified for the Vertical Blank.
Horizontal
Gating
Signal Width = [REG(16) – REG(15)] × ckper
Vertical
Gating
Signal Width = [REG(18) – REG(17)] × hper
Addressing Logic
The register addressing logic is composed of two blocks
of logic. The first is the address register and counter
(ADDRCNTR), and the second is the address decode
(ADDRDEC).
ADDRCNTR Logic
Addresses for the data registers can be generated by
one of two methods. Manual addressing requires that
each byte of each register that needs to be loaded needs
to be addressed. To load both bytes of all 19 registers
would require a total of 57 load cycles (19 address and
38 data cycles). Auto Addressing requires that only the
initial register value be specified. The Auto Load
sequence would require only 39 load cycles to com-
pletely program all registers (1 address and 38 data
cycles). In the auto load sequence the low order byte of
the data register will be written first followed by the high
order byte on the next load cycle. At the time the High
8
Cursor Position and Vertical Interrupt
The Cursor Position and Vertical Interrupt signal are
available when Composite Sync and Blank signals are
selected and Bit 2 of the Status Register is set to the
value of 1. The Cursor Position generates a single pulse
of n clocks wide during every line that the cursor is spec-
ified. The signals are generated by logically ORing
(ANDing) the active LOW (HIGH) signals specified by
the registers used for generating Horizontal and Vertical
Gating signals. The Vertical Interrupt signal generates a
pulse during the vertical interval specified. The Vertical
Interrupt signal will change in the same manner as that
specified for the Vertical Blanking signal.
Horizontal Cursor Width = [REG(16) – REG(15)] × ckper
Vertical Cursor Width = [REG(18) – REG(17)] × hper
Vertical Interrupt Width = [REG(14) – REG(13)] × hper
Byte is written the address counter is incremented by 1.
The counter has been implemented to loop on the initial
value loaded into the address register. For example: If a
value of 0 was written into the address register then the
counter would count from 0 to 18 before resetting back
to 0. If a value of 15 was written into the address register
then the counter would count from 15 to 18 before loop-
ing back to 15. If a value greater than or equal to 18 is
placed into the address register the counter will continu-
ously loop on this value. Auto addressing is initiated on
the falling edge of LOAD when ADDRDATA is 0 and
LHBYTE is 1. Incrementing and loading of data registers
will not commence until the falling edge of LOAD after
ADDRDATA goes to 1. The next rising edge of LOAD
will load the first byte of data. Auto Incrementing is dis-
abled on the falling edge of LOAD after ADDRDATA and
LHBYTE goes low.
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