74ACT715 Fairchild Semiconductor, 74ACT715 Datasheet
74ACT715
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74ACT715 Summary of contents
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... M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74ACT715-RPC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. ...
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Logic Block Diagram Pin Description There are a Total of 13 inputs and 5 outputs on the ACT715. Data Inputs D0–D7: The Data Input pins connect to the Address Register and the Data Input Register. ADDR/DATA: The ADDR/DATA signal is ...
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Register Description All of the data registers are 12 bits wide. Width’s of all pulses are defined by specifying the start count and end count of all pulses. Horizontal pulses are specified with- respect-to the number of clock pulses per ...
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Signal Specification HORIZONTAL SYNC AND BLANK SPECIFICATIONS All horizontal signals are defined by a start and end time. The start and end times are specified in number of clock cycles per line. The start of the horizontal line is considered ...
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FIGURE 2. Vertical Waveform Specification FIGURE 3. Equalization/Serration Interval Programming HORIZONTAL AND VERTICAL GATING SIGNALS Horizontal Drive and Vertical Drive outputs can be utilized as general purpose Gating Signals. Horizontal and Vertical Gating Signals are available for use when Composite ...
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Addressing Logic The register addressing logic is composed of two blocks of logic. The first is the address register and counter (ADDRCNTR), and the second is the address decode (ADDRDEC). ADDRCNTR LOGIC Addresses for the data registers can be generated ...
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ADDRDEC LOGIC The ADDRDEC logic decodes the current address and generates the enable signal for the appropriate register. The enable values for the registers and counters change on the falling edge of LOAD. Two types of ADDRDEC logic is enabled ...
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RS170 Default Register Values The tables below show the values programmed for the RS170 Format (using a 14.31818 MHz clock signal) and how they compare against the actual EIA RS170 Specifica- tions. The default signals that will be output are ...
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Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...
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AC Electrical Characteristics Symbol Parameter f Interlaced f MAXI max (HMAX/2 is ODD) f Non-Interlaced f max max (HMAX/2 is EVEN) t Clock to Any Output PLH1 t PHL1 t Clock to ODDEVEN PLH2 t (Scan Mode) PHL2 t Load ...
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Capacitance (Continued) Additional Applications Information POWERING UP The ACT715 default value for Bit 10 of the Status Register is 0. This means that when the CLEAR pulse is applied and the registers are initialized by loading the default values the ...
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FIGURE 6. Default RS170 Hardwire Configuration Note: A 74HC221A may be substituted for the 74HC423A Pin 6 and Pin 14 must be hardwired to GND Components R1: 4.7k C1 R2:10k C2 FIGURE 7. Circuit for Clear ...
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Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B 13 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE ...