74ACT715SCNL Fairchild Semiconductor, 74ACT715SCNL Datasheet - Page 11

• Manufacturer Part Number: 74ACT715SCNL
• Manufacturer: Fairchild Semiconductor

Specifications of 74ACT715SCNL

• Lead Free Status / RoHS Status: Compliant

©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
than 12 CLOCK pulses on the same register will only
cause the MSB to repeat on the output. Re-scanning the
same register will require that register to be reloaded.
The value of the two horizontal counters and 1 vertical
counter can also be scanned out by using address num-
bers 51–53. Note that before the part will scan out the
data, the LOAD signal must be brought back HIGH.
RS170 Default Register Values
The tables below show the values programmed for the
RS170 Format (using a 14.31818 MHz clock signal) and
how they compare against the actual EIA RS170 Specifi-
cations. The default signals that will be output are
CSYNC, CBLANK, HDRIVE and VDRIVE. The device
initially starts at the beginning of the odd field of inter-
REG10
REG11
REG12
REG13
REG14
REG15
REG16
REG17
REG18
REG0
REG0
REG1
REG2
REG3
REG4
REG5
REG6
REG7
REG8
REG9
Reg
Input Clock
Line Rate
Field Rate
Frame Rate
1024
157
910
525
410
526
911
23
91
13
41
57
19
41
92
21
0
7
1
1
D Value H
05B
09D
38E
00D
20D
19A
20E
05C
000
400
017
007
029
039
001
013
029
38F
001
015
Rate
14.31818MHz
15.73426kHz
59.94Hz
29.97Hz
Status Register (715)
Status Register (715-R)
HFP End Time
HSYNC Pulse End Time
HBLANK Pulse End Time
Total Horizontal Clocks
VFP End Time
VSYNC Pulse End Time
VBLANK Pulse End Time
Total Vertical Lines
Equalization Pulse End Time
Serration Pulse Start Time
Pulse Interval Start Time
Pulse Interval End Time
Vertical Interrupt Activate Time
Vertical Interrupt Deactivate Time
Horizontal Drive Start Time
Horizontal Drive End Time
Vertical Drive Start Time
Vertical Drive End Time
11
Normal device operation can be resumed by loading in a
non-scan address. As the scanning of the registers is a
non-destructive scan, the device will resume correct
operation from the point at which it was halted.
lace. All signals have active low pulses and the clock is
disabled at power up. Registers 13 and 14 are not
involved in the actual signal information. If the Vertical
Interrupt was selected so that a pulse indicating the
active lines would be output.
Register Description
69.841ns
63.556µs
16.683ms
33.367ms
Period
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