74ACT715SCNL Fairchild Semiconductor, 74ACT715SCNL Datasheet - Page 6

• Manufacturer Part Number: 74ACT715SCNL
• Manufacturer: Fairchild Semiconductor

Specifications of 74ACT715SCNL

• Lead Free Status / RoHS Status: Compliant

©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
CURSOR LOCATION REGISTERS
These 4 registers determine the cursor position location,
or they generate separate Horizontal and Vertical Gating
signals.
REG15— Horizontal Cursor Position Start Time
REG16— Horizontal Cursor Position End Time
REG17— Vertical Cursor Position Start Time
REG18— Vertical Cursor Position End Time
Signal Specification
Horizontal Sync and Blank Specifications
All horizontal signals are defined by a start and end time.
The start and end times are specified in number of clock
cycles per line. The start of the horizontal line is consid-
ered pulse 1 not 0. All values of the horizontal timing reg-
isters are referenced to the falling edge of the Horizontal
Blank signal (See Figure 2). Since the first CLOCK edge,
CLOCK #1, causes the first falling edge of the Horizontal
Blank reference pulse, edges referenced to this first
Horizontal edge are n + 1 CLOCKs away, where “n” is
the width of the timing in question. Registers 1, 2, and 3
are programmed in this manner. The horizontal counters
start at 1 and count until HMAX. The value of HMAX
must be divisible by 2. This limitation is imposed because
during interlace operation this value is internally divided
by 2 in order to generate serration and equalization
pulses at 2 × the horizontal frequency. Horizontal signals
will change on the falling edge of the CLOCK signal.
Signal specifications are shown below.
Horizontal Period (HPER) = REG(4) × ckper
Horizontal Blanking Width = [REG(3) – 1] × ckper
Horizontal Sync Width = [REG(2) – REG(1)] × ckper
Horizontal Front Porch = [REG(1) – 1] × ckper
Vertical Sync and Blank Specifications
All vertical signals are defined in terms of number of
lines per frame. This is true in both interlaced and nonin-
terlaced modes of operation. Care must be taken to not
specify the Vertical Registers in terms of lines per field.
Since the first CLOCK edge, CLOCK #1, causes the first
falling edge of the Vertical Blank (first Horizontal Blank)
reference pulse, edges referenced to this first edge are n
+ 1 lines away, where “n” is the width of the timing in
question. Registers 5, 6, and 7 are programmed in this
manner. Also, in the interlaced mode, vertical timing is
based on half-lines. Therefore registers 5, 6, and 7 must
contain a value twice the total horizontal (odd and even)
plus 1 (as described above). In non-interlaced mode, all
vertical timing is based on whole-lines. Register 8 is
6
always based on whole-lines and does not add 1 for the
first clock. The vertical counter starts at the value of 1
and counts until the value of VMAX. No restrictions exist
on the values placed in the vertical registers. Vertical
Blank will change on the leading edge of HBLANK. Verti-
cal Sync will change on the leading edge of HSYNC.
(See Figure 3.) Vertical Frame Period (VPER) = REG(8)
× hper
Vertical Field Period (VPER/n) = REG(8) × hper/n
Vertical Blanking Width = [REG(7) – 1] × hper/n
Vertical Syncing Width = [REG(6) – REG(5)] × hper/n
Vertical Front Porch = [REG(5) – 1] × hper/n
where,
n = 1 for noninterlaced
n = 2 for interlaced
Composite Sync and Blank Specifications
Composite Sync and Blank signals are created by logi-
cally ANDing (ORing) the active LOW (HIGH) signals of
the corresponding vertical and horizontal components of
these signals. The Composite Sync signal may also
include serration and/or equalization pulses. The Serra-
tion pulse interval occurs in place of the Vertical Sync
interval. Equalization pulses occur preceding and/or
following the Serration pulses. The width and location of
these pulses can be programmed through the registers
shown below. (See Figure 4.)
Horizontal
Equalization PW = [REG(9) – REG(1)] × ckper
REG 9 = (HFP) + (HEQP) + 1
Horizontal
Serration PW = [REG(4)/n + REG(1) – REG(10)] × ckper
REG 10 = (HFP) + (HPER/2) – (HSERR) + 1
where,
n = 1 for noninterlaced single serration/equalization
n = 2 for noninterlaced double serration/equalization
n = 2 for interlaced operation
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