MT48LC2M32B2P-6:G Micron Technology Inc, MT48LC2M32B2P-6:G Datasheet - Page 17

• Manufacturer Part Number: MT48LC2M32B2P-6:G
• Description: IC, SDRAM, 64MBIT, 166MHZ, TSOP-86
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC2M32B2P-6:G

• Organization: 2Mx32
• Density: 64Mb
• Address Bus: 13b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 180mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Type: DRAM - Sychronous
• Access Time: 5.5ns
• Page Size: 64Mbit
• Memory Case Style: TSOP
• No. Of Pins: 86
• Operating Temperature Range: 0°C To +70°C
• Frequency: 166MHz
• Supply Voltage: 3.3V
• Format - Memory: RAM
• Memory Size: 64M (2Mx32)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 86-TFSOP (0.400", 10.16mm Width)
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Commands
Table 7:
COMMAND INHIBIT
NO OPERATION (NOP)
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. M 10/07 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ
(Select bank and column, and start READ burst)
WRITE
(Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE
(Deactivate row in bank or banks)
AUTO REFRESH or SOFT REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
Truth Table 1 – Commands and DQM Operation
CKE is HIGH for all commands shown except SELF REFRESH.
Notes:
Truth Table 1 provides a quick reference of available commands. This is followed by a
written description of each command. Three additional Truth Tables appear following
“Operation” on page 20; these tables provide current state/next state information.
1. A0–A11 define the op-code written to the mode register.
2. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
3. A0–A9 (x4), A0–A8 (x8), or A0–A7 (x16) provide column address; A10 (HIGH) enables the
4. A10 (LOW): BA0, BA1 determine the bank being precharged. A10 HIGH: All banks pre-
5. This command is AUTO REFRESH if CKE is (HIGH), SELF REFRESH if CKE is LOW.
6. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
The command inhibit function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM that is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
auto precharge feature (nonpersistent), while A10 (LOW) disables the auto precharge fea-
ture; BA0, BA1 determine which bank is being read from or written to.
charged and BA0, BA1 are “Don’t Care.”
for CKE.
delay).
CS#
H
L
L
L
L
L
L
L
–
–
L
17
RAS# CAS#
H
H
H
H
X
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
L
L
L
L
–
–
WE#
X
H
H
H
H
L
L
L
L
–
–
DQM
L/H8
L/H8
64Mb: x4, x8, x16 SDRAM
X
X
X
X
X
X
X
H
L
Bank/row
Bank/col
Bank/col
Op-code
©2000 Micron Technology, Inc. All rights reserved.
ADDR
Code
X
X
X
X
–
–
High-Z
Active
Active
Valid
Commands
DQs
X
X
X
X
X
X
X
Notes
5, 6
2
3
3
4
1
7
7