S71PL064JB0BFW0B0 Spansion Inc., S71PL064JB0BFW0B0 Datasheet - Page 7

• Manufacturer Part Number: S71PL064JB0BFW0B0
• Manufacturer: Spansion Inc.

Specifications of S71PL064JB0BFW0B0

• Operating Supply Voltage (max): 3.1V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Functional Description . . . . . . . . . . . . . . . . . . . . . 162
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 162
DC Characteristics (4Mb pSRAM
Asynchronous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
DC Characteristics (8Mb pSRAM
Asynchronous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
DC Characteristics (16Mb pSRAM
Asynchronous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
DC Characteristics (16Mb pSRAM Page Mode) . 166
DC Characteristics (32Mb pSRAM Page Mode) . 167
DC Characteristics (64Mb pSRAM Page Mode) 168
Timing Test Conditions . . . . . . . . . . . . . . . . . . . 168
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . 169
AC Characteristics (4Mb pSRAM Page Mode) . 170
AC Characteristics (8Mb pSRAM
Asynchronous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
AC Characteristics (16Mb pSRAM
Asynchronous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
AC Characteristics (16Mb pSRAM Page Mode) . 176
7
Data Retention Characteristics (4M Version F) ...................................... 156
Data Retention Characteristics (4M Version G) .................................... 157
Data Retention Characteristics (8M Version C) .................................... 157
Data Retention Characteristics (8M Version D) .................................... 157
Timing Diagrams ................................................................................................ 157
Output Load Circuit ........................................................................................ 169
Figure 73. Timing Waveform of Read Cycle(1) (Address Controlled,
CS#1=OE#=V
Figure 74. Timing Waveform of Read Cycle(2) (WE#=V
is Low, Ignore UB#/LB# Timing) ........................................ 158
Figure 75. Timing Waveform of Write Cycle(1) (WE# controlled, if
BYTE# is Low, Ignore UB#/LB# Timing).............................. 158
Figure 76. Timing Waveform of Write Cycle(2) (CS# controlled, if
BYTE# is Low, Ignore UB#/LB# Timing).............................. 159
Figure 77. Timing Waveform of Write Cycle(3) (UB#, LB#
controlled) ...................................................................... 159
Figure 78. Data Retention Waveform .................................. 160
Figure 79. Output Load Circuit ........................................... 169
IL
, CS2=WE#=V
pSRAM Type 1
IH
, UB# and/or LB#=V
IL
A d v a n c e
IH
)....... 157
, if BYTE#
AC Characteristics (32Mb pSRAM Page Mode) 178
AC Characteristics (64Mb pSRAM Page Mode) 180
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 181
Power Savings Modes (For 16M Page Mode, 32M and
64M Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Mode Register Update and Deep Sleep
Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Address Patterns for PASR (A4=1) (64M) . . . . . 189
Deep ICC Characteristics (for 64Mb) . . . . . . . . . 190
Address Patterns for PAR (A3= 0, A4=1) (32M) . 190
Address Patterns for RMS (A3 = 1, A4 = 1)
(32M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Low Power ICC Characteristics (32M) . . . . . . . . 191
Address Patterns for PAR (A3= 0, A4=1) (16M) . 191
Address Patterns for RMS (A3 = 1, A4 = 1) (16M) 191
Low Power ICC Characteristics (16M) . . . . . . . . 191
Read Cycle ............................................................................................................181
Write Cycle .........................................................................................................184
Partial Array Self Refresh (PAR) ...................................................................185
Temperature Compensated Refresh (for 64Mb) ....................................186
Deep Sleep Mode ..............................................................................................186
Reduced Memory Size (for 32M and 16M) .................................................186
Other Mode Register Settings (for 64M) ...................................................186
I n f o r m a t i o n
Figure 80. Timing of Read Cycle (CE# = OE# = V
V
Figure 81. Timing Waveform of Read Cycle
(WE# = ZZ# = V
Figure 82. Timing Waveform of Page Mode Read Cycle
(WE# = ZZ# = V
Figure 83. Timing Waveform of Write Cycle
(WE# Control, ZZ# = V
Figure 84. Timing Waveform of Write Cycle
(CE# Control, ZZ# = V
Figure 85. Timing Waveform of Page Mode Write Cycle
(ZZ# = V
Figure 86. Mode Register .................................................. 187
Figure 87. Mode Register Update Timings (UB#, LB#, OE# are
Don’t Care)..................................................................... 187
Figure 88. Deep Sleep Mode - Entry/Exit Timings................. 188
IH
) ............................................................................... 181
IH
) ................................................................... 185
Revision Summary
IH
IH
)......................................................... 182
)......................................................... 183
IH
IH
S71PL254/127/064/032J_00A5 September 14, 2004
)................................................. 184
)................................................ 184
IL
, WE# = ZZ# =