S71PL064JB0BFW0B0 Spansion Inc., S71PL064JB0BFW0B0 Datasheet - Page 5

• Manufacturer Part Number: S71PL064JB0BFW0B0
• Manufacturer: Spansion Inc.

Specifications of S71PL064JB0BFW0B0

• Operating Supply Voltage (max): 3.1V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Write Operation Status . . . . . . . . . . . . . . . . . . . . 76
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .82
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .83
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .84
AC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . .85
Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 94
BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 98
5
Command Definitions Tables ..........................................................................74
DQ7: Data# Polling ............................................................................................76
DQ6: Toggle Bit I ............................................................................................... 78
DQ2: Toggle Bit II ...............................................................................................79
Reading Toggle Bits DQ6/DQ2 ......................................................................79
DQ5: Exceeded Timing Limits ....................................................................... 80
DQ3: Sector Erase Timer ................................................................................ 80
Industrial (I) Devices ..........................................................................................83
Extended (E) Devices .........................................................................................83
Supply Voltages ....................................................................................................83
Test Conditions .................................................................................................. 85
SWITCHING WAVEFORMS ......................................................................... 86
VCC RampRate .................................................................................................. 86
Read Operations ................................................................................................ 87
Reset ......................................................................................................................88
Erase/Program Operations ............................................................................. 90
Timing Diagrams .................................................................................................. 91
Controlled Erase Operations ......................................................................... 96
Table 17. Memory Array Command Definitions ...................... 74
Table 18. Sector Protection Command Definitions .................. 75
Figure 6. Data# Polling Algorithm......................................... 77
Figure 7. Toggle Bit Algorithm.............................................. 79
Table 19. Write Operation Status ......................................... 81
Figure 8. Maximum Overshoot Waveforms............................. 82
Table 20. CMOS Compatible ................................................ 84
Figure 9. Test Setups......................................................... 85
Table 21. Test Specifications ............................................... 85
Table 22. KEY TO SWITCHING WAVEFORMS ......................... 86
Figure 10. Input Waveforms and Measurement Levels............. 86
Table 23. Read-Only Operations .......................................... 87
Figure 11. Read Operation Timings ....................................... 87
Figure 12. Page Read Operation Timings ............................... 88
Table 24. Hardware Reset (RESET#) .................................... 88
Figure 13. Reset Timings..................................................... 89
Table 25. Erase and Program Operations .............................. 90
Figure 14. Program Operation Timings .................................. 91
Figure 15. Accelerated Program Timing Diagram .................... 91
Figure 16. Chip/Sector Erase Operation Timings ..................... 92
Figure 17. Back-to-back Read/Write Cycle Timings ................. 92
Figure 18. Data# Polling Timings (During Embedded Algorithms) .
93
Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 93
Figure 20. DQ2 vs. DQ6 ...................................................... 94
Table 26. Temporary Sector Unprotect ................................. 94
Figure 21. Temporary Sector Unprotect Timing Diagram.......... 94
Figure 22. Sector/Sector Block Protect and Unprotect Timing
Diagram............................................................................ 95
Table 27. Alternate CE# Controlled Erase and Program Operations
96
Table 28. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ............................................................. 97
Table 29. Erase And Programming Performance .................... 98
Type 2 pSRAM
A d v a n c e
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Product Information . . . . . . . . . . . . . . . . . . . . . . 100
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 101
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 102
Functional Description . . . . . . . . . . . . . . . . . . . . . 102
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 103
DC Recommended Operating Conditions . . . . . 103
Capacitance (Ta = 25°C, f = 1 MHz) . . . . . . . . . . 103
DC and Operating Characteristics . . . . . . . . . . . 103
AC Operating Conditions . . . . . . . . . . . . . . . . . . 105
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 107
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Absolute Maximum Ratings (see Note) . . . . . . . 111
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 111
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 112
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 114
Power Up .............................................................................................................102
Common ..............................................................................................................103
16M pSRAM ..........................................................................................................104
32M pSRAM .........................................................................................................104
64M pSRAM .........................................................................................................105
Test Conditions (Test Load and Test Input/Output Reference) ........105
ACC Characteristics (Ta = -40°C to 85°C, V
Read Timings .......................................................................................................107
Write Timings .................................................................................................... 108
I n f o r m a t i o n
Figure 23. Power Up 1 (CS1# Controlled) ........................... 102
Figure 24. Power Up 2 (CS2 Controlled).............................. 102
Figure 25. Output Load .................................................... 105
Figure 26. Timing Waveform of Read Cycle(1) ..................... 107
Figure 27. Timing Waveform of Read Cycle(2) ..................... 107
Figure 28. Timing Waveform of Read Cycle(2) ..................... 107
Figure 29. Write Cycle #1 (WE# Controlled)........................ 108
Figure 30. Write Cycle #2 (CS1# Controlled) ...................... 108
Figure 31. Timing Waveform of Write Cycle(3) (CS2 Controlled) ...
109
Figure 32. Timing Waveform of Write Cycle(4) (UB#, LB#
Controlled) ..................................................................... 109
Table 30. DC Recommended Operating Conditions ............... 111
Table 31. DC Characteristics (T
3.3V) ............................................................................. 112
Table 32. AC Characteristics and Operating Conditions (T
to 85°C, V
Table 33. AC Test Conditions ............................................. 113
Figure 33. AC Test Loads .................................................. 113
Figure 34. State Diagram ................................................. 114
Table 34. Standby Mode Characteristics .............................. 114
Figure 35. Read Cycle 1—Addressed Controlled ................... 114
Figure 36. Read Cycle 2—CS1# Controlled.......................... 115
Figure 37. Write Cycle 1—WE# Controlled .......................... 115
Figure 38. Write Cycle 2—CS1# Controlled ......................... 116
Figure 39. Write Cycle3—UB#, LB# Controlled .................... 116
Figure 40. Deep Power-down Mode .................................... 117
Figure 41. Power-up Mode ................................................ 117
Figure 42. Abnormal Timing .............................................. 117
DD
= 2.6 to 3.3V) .............................................. 112
pSRAM Type 3
S71PL254/127/064/032J_00A5 September 14, 2004
A
= -25°C to 85°C, VDD = 2.6 to
CC
= 2.7 to 3.1 V) ........106
A
= -25°C