S71PL064JB0BFW0B0 Spansion Inc., S71PL064JB0BFW0B0 Datasheet - Page 184
S71PL064JB0BFW0B0
Manufacturer Part Number
S71PL064JB0BFW0B0
Description
Manufacturer
Spansion Inc.
Datasheet
1.S71PL064JB0BFW0B0.pdf
(189 pages)
Specifications of S71PL064JB0BFW0B0
Operating Supply Voltage (max)
3.1V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Mode Register Update and Deep Sleep Timings
Notes:
1. Minimum cycle time for writing register is equal to speed grade of product.
Address Patterns for PASR (A4=1) (64M)
189
Chip deselect to ZZ# low
ZZ# low to WE# low
Write register cycle time
Chip enable to end of write
Address valid to end of write
Write recovery time
Address setup time
Write pulse width
Deep Sleep Pulse Width
Deep Sleep Recovery
A2 A1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
A0
1
0
1
0
1
0
1
0
Item
Bottom quarter of die
Top quarter of die
Bottom half of die
Top half of die
Active Section
Reserved
Reserved
Full array
No PASR
Symbol
t
t
t
ZZMIN
ZZWE
CDZZ
t
t
t
t
t
t
WC
CW
AW
WR
WR
t
pSRAM Type 1
AS
R
P r e l i m i n a r y
300000h-3FFFFFh
200000h-3FFFFFh
000000h-0FFFFFh
000000h-1FFFFFh
000000h-3FFFFFh
Address Space
70/85
70/85
70/85
150
Min
10
40
10
None
5
0
0
Max
500
pSRAM_Type01_12_A0 June 8, 2004
1Mb x 16
2Mb x 16
1Mb x 16
2Mb x 16
4Mb x 16
Size
Unit
0
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Note
Density
16Mb
32Mb
16Mb
32Mb
64Mb
1
1
1
0
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