82V1074PF IDT, Integrated Device Technology Inc, 82V1074PF Datasheet - Page 90

• Manufacturer Part Number: 82V1074PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1074PF

• Number Of Channels: 4
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Operating Current: 95mA
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Lead Free Status / RoHS Status: Not Compliant

on-hook. In this mode, only the AC loop is active, all functions except for
the off-hook detection are switched off. The sensed voltage from the
RSLIC is fed to an analog comparator in the CODEC via VTAC pin. The
loop state can be determined by comparing the sensed voltage with a
fixed off-hook threshold. If off-hook state is detected, the overall circuits
should be activated and switched to the active mode.
mode, both AC and DC loops are active. The RSLIC provides low-
impedance voltage (VBL) fed to the line. The RSLIC senses the
transversal and longitudinal line currents and separates the transversal
current to AC and DC parts. The CODEC scales the currents and
converts the AC part of the transversal current to voice data. On the
other hand, the CODEC expands the voice data from the PCM bus and
converts them to an analog signal. The DC voltage fed to the line can be
automatically achieved by the chipset according to certain loop lengths,
power optimized solution.
provides both internal ringing and external ringing modes to be selected.
Refer to
signal of up to 70 Vp (for IDT82V1671A) or 52 Vp (for IDT82V1671) can
be generated without any external components. In applications that high
ringing voltage is not needed, a DC offset can be added to support the
DC ring trip detection, which is more reliable than AC ring trip detection.
be switched to power down mode. An individual operation amplifier in
the RSLIC is supplied for ring trip detection.
generator in the CODEC is active and able to generate a ramp signal to
help measuring the capacitance. The ramp generator is fully
programmable. By programming the ramp slope, ramp start voltage and
end voltage, a desired ramp can be generated by the CODEC and
output to the line via the RLSIC. With this ramp signal as the source, the
line capacitance can be measured via the DC level meter. See
Capacitance Measurement” on page 47
RSLIC & CODEC CHIPSET
• Standby
The standby mode is applicable for system state of subscriber being
• Active
The active mode corresponds to the system state of off-hook. In this
• Ring
This mode corresponds to the system state of ringing. The chipset
If internal ringing mode is selected, an internal balanced ringing
If an external ring generator and ring relays are used, the RSLIC can
• Ramp
If ramp mode is selected (LREG6: RAMP = 1), the integrated ramp
IO
FS
Table - 26
for details.
D
Q
for detailed information.
D
Q
Figure - 41 IO Debounce Filter
“3.9.6.5
D
90
Debounce Period
DB_IO[3:0]
(0 − 30ms)
6.2
the CODEC to reduce the power consumption. If the PLL_PD bit is set to
1, the PLL block is turned off and the DSP operation is disabled. As
described above, each of the channels can be individually powered
down by setting the corresponding P_DOWN bit in LREG6 to 1. When
all four channels and the PLL block are powered down, the lowest power
consumption can be achieved.
6.3
shown in the following:
or output by the corresponding control bits IO_C[3] to IO_C[0] in
LREG20.
indicated by the IO[3:0] bits in LREG20. If the IO pins are configured as
outputs, the data written in the IO[3:0] bits in LREG20 will be sent out
through the IO pins.
driving external relays. Based on this, the IO1 pin automatically acts as
an output to control the external ring relay when external ringing mode is
selected. Refer to
receiving analog inputs. With this capability external voltages can be fed
to the DC level meter via the IO3 and/or IO4 pins to be measured. Refer
to
debounce filter (see
remains in its present state unless the input remains in the opposite
state for the entire period of time programmed by the DB_IO[3:0] bits in
LREG11. The debounce period is programmable from 0 ms to 30 ms in
steps of 2 ms, corresponding to the minimal debounce time of 2.5 ms to
32.5 ms (a delay time of about 2.5 ms added). The default value of
DB_IO[3:0] is ‘0000’.
“3.9.6.6 Voltage Measurement” on page 48
The PLL_PD bit in GREG1 is used to power down the PLL block of
The CODEC provides four programmable IO pins per channel as
IO1:
IO2:
IO3:
IO4:
The four IO pins IO4 to IO1 can be independently configured as input
If the IO pins are configured as inputs, the status of the IO pins will be
If the IO1 and IO2 pins are configured as outputs, they are capable of
If the IO3 and IO4 pins are configured as inputs, they are capable of
The input signals from the four IOs will be filtered by a programmable
Q
PLL POWER DOWN
PROGRAMMABLE I/OS OF THE CODEC
D
“3.4.2 External Ringing Mode” on page 24
RST
IO pin with relay-driving capability
IO pin with relay-driving capability
IO pin with analog input capability
IO pin with analog input capability
Figure -
Q
IDT82V1671/IDT82V1671A, IDT82V1074
8 bit Debounce
Counter
41). The output of the debounce filter
D
En
Q
for details.
Debounced IO
for details.