82V1074PF IDT, Integrated Device Technology Inc, 82V1074PF Datasheet - Page 14

• Manufacturer Part Number: 82V1074PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1074PF

• Number Of Channels: 4
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Operating Current: 95mA
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Lead Free Status / RoHS Status: Not Compliant

DCL/BCLK
RSLIC & CODEC CHIPSET
CCLK/S0
MPI/GCI
DX1/DU
DR1/DD
INT/INT
RSYNC
RESET
VDDA1
VDDA2
VDDA3
VDDA4
MCLK
VDDD
Name
TSX1
TSX2
CI/S1
TEST
VCM
FSC
DX2
DR2
CNF
M1
M2
M3
CO
CS
Power
Power
Type
I/O
O
O
O
O
O
O
O
O
O
−
I
I
I
I
I
I
I
I
I
I
I
I
Pin Number
71, 53
54
55
56
60
75
76
69
70
68
72
73
74
62
64
63
61
66
77
17
67
59
57
15
30
18
90
2
RSLIC operating mode control output 1. The M1to M3 pins together with the CSn pin (n = 1 to 4 for Channel 1 to 4 respectively)
determine the operating mode of the RSLIC connected to Channel n of the CODEC. Refer to the description of the CSn pin for
details.
RSLIC operating mode control output 2. See the description of the M1 pin for details.
RSLIC operating mode control output 3 or RSLIC temperature information input. The direction of this pin is determined by the
logic level of the CSn pin (n = 1 to 4 for Channel 1 to 4 respectively):
CSn = 0: M3 is an output pin. It, together with M1 and M2, carries the mode control data to RSLICn;
CSn = 1: M3 is an input pin, carrying the temperature information of RSLICn to the CODEC.
Interface mode selection. Logic 0 selects MPI mode and logic 1 selects GCI mode.
Frame Synchronization Clock for PCM or GCI interface. The FSC signal is 8 kHz, identifying the beginning of the PCM frame
(MPI mode) or indicating the beginning of Time Slot 0 in GCI frame (GCI mode).
PCM Bit Clock (BCLK) for MPI mode or Data Clock (DCL) for GCI mode.
In MPI mode, the PCM data is transferred between the CODEC and the PCM highway, following the BCLK. The BCLK signal
and the MCLK signal should be from the same clock source. The BCLK signal is required to be synchronous to the FSC. The
frequency of the BCLK can be from 256 kHz to 8.192 MHz in steps of 64 kHz.
In GCI mode, the DCL is either 2.048 MHz or 4.096 MHz. The internal circuit of the CODEC automatically monitors this input to
determine which frequency is being used.
Data Transmit PCM highway one (for MPI mode) or Data Upstream (for GCI mode).
In MPI mode, the PCM data is transmitted to the PCM highway one (DX1) or two (DX2), following the BCLK.
In GCI mode, the GCI data of all four channels is transmitted via the DU pin to the master device.
Data Receive PCM highway one (for MPI mode) or Data Downstream (for GCI mode).
In MPI mode, the PCM Data is received from PCM highway one (DR1) or two (DR2), following the BCLK.
In GCI mode, the GCI data is received from the master device via the DD pin.
Transmit Indicator for PCM highway one, open drain. This pin becomes low when the data is transmitted via DX1.
Transmit Indicator for PCM highway two, open drain. This pin becomes low when the data is transmitted via DX2.
Data Transmit PCM highway two (for MPI mode). Refer to the description of the DX1 pin for details.
Data Receive PCM highway two (for MPI mode). Refer to the description of the DR1 pin for details.
Control Clock (CCLK) for MPI mode or Time Slot Selection 0 (S0) for GCI mode.
In MPI mode, the CCLK pin provides clock for the serial control interface. The frequency of the CCLK can be up to 8.192 MHz.
In GCI mode, the S0 together with Time Slot Selection 1 (S1) determines which time slot is used to transmit the voice or control
data.
Control Data Output (CO) for MPI mode.
Control Data Input (CI) for MPI mode or Time Slot Selection 1 (S1) for GCI mode.Refer to the description of the S0 pin for
details.
CODEC Chip Selection signal for MPI mode, active low.
Master Clock input. The MCLK pin provides the clock for the DSP of the CODEC. The frequency of the MCLK can be 1.536
MHz, 1.544 MHz, 2.048 MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz, 6.144 MHz, 6.176 MHz or 8.192 MHz.
In MPI mode, the MCLK signal and the BCLK signal should be from the same clock source.
Interrupt output pin for MPI mode. The active level of this pin is programmable. If any of the active interrupts occurs, this pin will
be set to active level, high or low. It is active low by default.
Reference voltage output. Typical 1.5 V.
Reset signal input. Active low.
External Ringing Synchronization signal. In external ringing mode, the synchronization signal provided by the external ringer is
applied to the CODEC via this pin. The external relay can be switched on or off by the IO1 pin synchronously following the
RSYNC.
Input pin for internal test purpose. This pin must be connected to the ground.
External capacitor connection. An external capacitor is connected between this pin and the AGND for noise filtering.
+3.3 V analog power supply.
+3.3 V digital power supply.
14
Description
IDT82V1671/IDT82V1671A, IDT82V1074