82V1074PF IDT, Integrated Device Technology Inc, 82V1074PF Datasheet - Page 56

• Manufacturer Part Number: 82V1074PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1074PF

• Number Of Channels: 4
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Operating Current: 95mA
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Lead Free Status / RoHS Status: Not Compliant

4.2.4
4.2.4.1
the chipset via the monitor channel. Using two monitor control bits MR
asynchronous basis:
Monitor Transmitter of the master device (DD MX bit is activated and set
to 0). This data transfer will be repeated within each frame (125 µs rate)
until it is acknowledged by the CODEC Monitor Receiver by setting the
DU MR bit to 0. Because of the handshaking protocol required for
successful communication, the data transfer rate using the monitor
channel is less than 8 kbit/s.
4.2.4.2
more consecutive frames signals an idle state on the monitor channel or
an end of message (EOM);
Transmitter, together with a data byte (can be changed) on the monitor
channel;
Monitor Receiver, together with a data byte remaining in the monitor
channel.
out an active MX bit (‘0’) together with the first byte of data to be
transmitted in the monitor channel. This state remains until the
addressed monitor receiver acknowledges the receipt of data by
RSLIC & CODEC CHIPSET
In GCI mode, upstream processors access the registers and RAM of
The transmission of the monitor channel is operated on a pseudo-
− Data transfer (bits) on the bus is synchronized to FSC;
− Data flow (bytes) are asynchronously controlled by the
For example: Data is placed onto the DD Monitor Channel by the
The monitor channel works in three states:
I. Idle state: Both the MR and MX bits are inactive (‘1’) during two or
II. Sending state: The MX bit is activated ('0') by the Monitor
III. Acknowledging: The MR bit is set to active state ('0') by the
A start of transmission is initiated by a monitor transmitter by sending
handshake procedure.
GCI MONITOR TRANSFER PROTOCOL
Monitor Channel Operation
Monitor Handshake Procedure
Transmitter
Receiver
Monitor
Monitor
Master Device
MX
MR
MR
MX
Figure - 33 Monitor Channel Operation
DD
DU
56
and MX per direction (the MR and MX bits are contained in the C/I
channel bytes), data is transferred between the upstream and
downstream devices in a complete handshake procedure.
shows the monitor channel operating diagram.
sending out an active MR bit (‘0’). The data transmission is repeated
each 125 µs frame (minimum is one repetition). During this time the
Monitor Transmitter keeps detecting the MR bit.
place when the transmitter’s MX bit and the receiver’s MR bit are in
active state.
twice (in two consecutive frames), a last look function is able to check for
data errors. If two different bytes are received the receiver will wait for
the receipt of two identical successive bytes.
implemented to avoid two or more devices are trying to send data at the
same time. The mechanism is realized by looking for the inactive (‘1’)
phase of the MX bit and making a per bit collision check on the
transmitted monitor data (check whether transmitted ‘1’s are on the DU/
DD line. The DU/DD line are open drain).
device is ready to receive new commands.
the falling edge of the receivers acknowledgment.
possible. It is not allowed to send any data to the CODEC while
transmission is active.
least according to the GCI monitor handshake procedure.
handshake procedure.
Flow control, means in the form of transmission delay, can only take
On the receiver side, since the monitor data can be received at least
On the transmitter side, a collision resolution mechanism is
Any abort leads to a reset of the CODEC command stack, and the
To obtain a maximum speed data transfer, the transmitter anticipates
Due to the inherent programming structure, duplex operation is not
Note that each byte on the monitor channel must be sent twice at
Refer to
Figure - 34
MX
MX
MR
MR
CODEC
IDT82V1671/IDT82V1671A, IDT82V1074
and
Transmitter
Receiver
Monitor
Monitor
Figure - 35
for details about monitor
Figure - 33