82V1074PF IDT, Integrated Device Technology Inc, 82V1074PF Datasheet - Page 55

• Manufacturer Part Number: 82V1074PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1074PF

• Number Of Channels: 4
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Operating Current: 95mA
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Lead Free Status / RoHS Status: Not Compliant

4.2.3
are continuously (every frame) carrying I/O information to and from the
CODEC. Real-time signaling information for the two channels (A & B)
are transferred via the six C/I bits. The two least significant bits of the C/
I bytes (MR and MX) are handshaking bits for the monitor channel. The
CODEC transmits or receives the C/I channel data with the most
significant bit first.
4.2.3.1
mode of the RSLIC. This byte is defined as:
The C
or Channel B respectively:
respective RSLIC. The SCAN_EN bit in this byte determines whether
the corresponding RSLIC will be accessed. Refer to
Operating Modes” on page 89
program the downstream C/I channel byte, users can configure the
operating mode of every channel as required.
MSB
RSLIC & CODEC CHIPSET
C
The downstream and upstream command/indication (C/I) channels
The downstream C/I channel byte is used to control the operating
This byte is shared by two channels (A & B) to transfer information.
C
C
The SM[2:0] bits are used to configure the operating mode of the
A
A
B
A
= 1: the control information carrying by the SCAN_EN and
= 1: the control information carrying by the SCAN_EN and
and C
C
SM[2:0] bits is for Channel A.
SM[2:0] bits is for Channel B.
B
COMMAND/INDICATION (C/I) CHANNEL
Downstream C/I Channel Byte
B
bits indicate whether the current C/I byte is for Channel A
SCAN_EN SM[2]
Downstream C/I Channel Byte
for detailed information. By properly
SM[1]
SM[0]
MR
“6.1.2 RSLIC
LSB
MX
55
4.2.3.2
information from the chipset to the master device. The definition of this
byte is as follows:
INT_POL bit in GREG24:
INT_CHA HOOKA GNDKA INT_CHB HOOKB GNDKB
MSB
The upstream C/I channel byte quickly transfers the most time-critical
The six C/I bits in this byte is illustrated below:
HOOKA:
HOOKA = 0:
HOOKA = 1:
HOOKB:
HOOKB = 0:
HOOKB = 1:
GNDKA:
GNDKA = 0:
GNDKA = 1:
GNDKB:
GNDKB = 0:
GNDKB = 1:
INT_CHA:
INT_CHB:
The valid polarity of INT_CHA and INT_CHB depends on the
INT_POL = 0: active low (default)
INT_POL = 1: active high
Upstream C/I Channel Byte
hook state of channel A
channel A is on-hook
channel A is off-hook
hook state of channel B
channel B is on-hook
channel B is off-hook
ground-key information of channel A
no longitudinal current is detected in channel A
longitudinal current is detected in channel A
ground-key information of channel B
no longitudinal current is detected in channel B
longitudinal current is detected in channel B
interrupt information of channel A
interrupt information of channel B
Upstream C/I Channel Byte
IDT82V1671/IDT82V1671A, IDT82V1074
MR
LSB
MX