PN5120A0HN1/C1 NXP Semiconductors, PN5120A0HN1/C1 Datasheet - Page 100

• Manufacturer Part Number: PN5120A0HN1/C1
• Description: RF Wireless Misc COMBO ANALOG/DIGI IC
• Manufacturer: NXP Semiconductors
• Type: Transmission Moduler

Specifications of PN5120A0HN1/C1

• Package / Case: HVQFN EP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 30 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PN5120A0HN1/C1,157

NXP Semiconductors
111334
Product data sheet
18.3.1.8 Transceive command
18.3.1.9 AutoColl command
This circular command repeats transmitting data from the FIFO and receiving data from
the RF field continuously. If the bit Initiator in the register ControlReg is set to logic 1, it
indicates that the first action is transmitting and after having finished transmission the
receiver is activated to receive data. If the bit Initiator in the register ControlReg is set to
logic 0, the first action is receiving and after having received a data stream, the transmitter
is activated to transmit data. In the second configuration the PN512 first acts as a receiver
and if a data stream is received it switches to the Transmit mode.
Each transmission process has to be started by setting bit StartSend in the register
BitFramingReg to 1. This command has to be cleared by software by writing any
command to the Command-register e.g. the command idle.
Note: If the bit RxMultiple in register RxModeReg is set to logic 1, this command will never
leave the receiving state, because the receiving will not be cancelled automatically.
This command automatically handles the MIFARE activation and the FeliCa polling in the
Card Operation mode. The bit Initiator in the register ControlReg has to be set to logic 0
for correct operation. During this command also the mode detector is active if not
deactivated by setting the bit ModeDetOff in the ModeReg register. After the mode
detector detects a mode, all the mode dependent registers are set according to the
received data. In case of no external RF field this command resets the internal state
machine and returns to the initial state but it will not be terminated. When the command
terminates the transceive command gets active.
During protocol processing the IRQ bits are not supported. Only the last received frame
will serve the IRQ's. The treatment of the TxCRCEn and RxCRCEn bits is different to the
protocol. During ISO/IEC 14443A activation the enable bits are defined by the command
AutoColl. The changes cannot be observed at the register TxModeReg and RxModeReg.
After the Transceive command is active, the value of the register bit is relevant.
Note: Pay attention, that the FIFO will also receive the two CRC check bytes of the last
command even if they are already checked and correct, if the state machine (Anticollision
and Select routine) has to not been executed, and 106 kbit is detected.
During Felica activation the register bit is always relevant and is not overruled by the
command settings.
This command can be cleared by software by writing any other command to the
CommandReg register, e.g. the idle command. Writing the same content again to the
CommandReg register resets the state machine.
Initiator =1
Send
Receive
Send
Receive
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Rev. 3.4 — 8 September 2009
Initiator=0
Receive
Send
Receive
Send
....
....
....
....
....
Transmission Module
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