PN5120A0HN1/C1 NXP Semiconductors, PN5120A0HN1/C1 Datasheet - Page 10

• Manufacturer Part Number: PN5120A0HN1/C1
• Description: RF Wireless Misc COMBO ANALOG/DIGI IC
• Manufacturer: NXP Semiconductors
• Type: Transmission Moduler

Specifications of PN5120A0HN1/C1

• Package / Case: HVQFN EP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 30 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PN5120A0HN1/C1,157

NXP Semiconductors
8. PN512 register SET
111334
Product data sheet
8.1 PN512 registers overview
Table 5.
Addr
(hex)
Page 0: Command and Status
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Page 1: Command
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Page 2: CFG
Register Name
PageReg
CommandReg
ComlEnReg
DivlEnReg
ComIrqReg
DivIrqReg
ErrorReg
Status1Reg
Status2Reg
FIFODataReg
FIFOLevelReg
WaterLevelReg
ControlReg
BitFramingReg
CollReg
RFU
PageReg
ModeReg
TxModeReg
RxModeReg
TxControlReg
TxAutoReg
TxSelReg
RxSelReg
RxThresholdReg Selects thresholds for the bit decoder
DemodReg
FelNFC1Reg
FelNFC2Reg
MifNFCReg
ManualRCVReg
TypeBReg
SerialSpeedReg
PN512 registers overview
Rev. 3.4 — 8 September 2009
Function
Selects the register page
Starts and stops command execution
Controls bits to enable and disable the passing of Interrupt Requests
Controls bits to enable and disable the passing of Interrupt Requests
Contains Interrupt Request bits
Contains Interrupt Request bits
Error bits showing the error status of the last command executed
Contains status bits for communication
Contains status bits of the receiver and transmitter
In- and output of 64 byte FIFO-buffer
Indicates the number of bytes stored in the FIFO
Defines the level for FIFO under- and overflow warning
Contains miscellaneous Control Registers
Adjustments for bit oriented frames
Bit position of the first bit collision detected on the RF-interface
Reserved for future use
Selects the register page
Defines general modes for transmitting and receiving
Defines the data rate and framing during transmission
Defines the data rate and framing during receiving
Controls the logical behavior of the antenna driver pins TX1 and TX2
Controls the setting of the antenna drivers
Selects the internal sources for the antenna driver
Selects internal receiver settings
Defines demodulator settings
Defines the length of the valid range for the receive package
Defines the length of the valid range for the receive package
Controls the communication in ISO/IEC 14443/MIFARE and NFC
target mode at 106 kbit
Allows manual fine tuning of the internal receiver
Configure the ISO/IEC 14443 type B
Selects the speed of the serial UART interface
Transmission Module
© NXP B.V. 2010. All rights reserved.
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