ATA5812-PLQW80 Atmel, ATA5812-PLQW80 Datasheet - Page 52

• Manufacturer Part Number: ATA5812-PLQW80
• Description: RF Transceiver RF Data Control Transceiver
• Manufacturer: Atmel

Specifications of ATA5812-PLQW80

• Wireless Frequency: 226 KHz
• Interface Type: 4-Wire SPI
• Noise Figure: 7 dB
• Output Power: 10 dBm
• Operating Supply Voltage: 2.4 V to 5.25 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-48
• Maximum Data Rate: 20 Kbps
• Minimum Operating Temperature: - 40 C
• Modulation: ASK, FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 11-2. Flow Chart Polling Mode/RX Mode (T_MODE = 1, Transparent Mode Active)
52
Sleep mode:
All circuits for analog signal processing are disabled. Only XTO and Polling logic is enabled.
Output level on pin RX_ACTIVE
T
Start-up mode:
Bit-check mode:
The incomming data stream is analyzed. If the timing indicates a valid transmitter signal,
the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the transceiver is set to
receiving mode. Otherwise the transceiver is set to Sleep mode
(if OPM0 = 0 and T
Output level on pin RX_ACTIVE
I
Receiving mode:
The incomming data stream is passed via PIN SDO_TMDO to the connected
microcontroller. If an bit error occurs the transceiver is not set back to Start-up mode.
Output level on pin RX_ACTIVE
I
S
S
Sleep
= I
= I
ATA5811/ATA5812
Start-up PLL:
The PLL is enabled and locked.
Output level on pin RX_ACTIVE
Start-up signal processing:
The signal processing circuit are enabled.
Output level on pin RX_ACTIVE
RX_X
RX_X
= Sleep
Start RX Mode
NO
; T
Bit-check
1024
T
Sleep
OPM0 = 1
SLEEP
?
?
T
> 0) or stays in Bit-check mode.
DCLK
YES
YES
= 0
Start RX Polling Mode
X
Sleep
Low; I
High
High
RX data stream
available on pin
NO
High; I
High; I
SDO_TMDO
Level on pin
CS = Low ?
S
= I
NO
S
S
IDLE_X
= I
= I
Startup_PLL_X
RX_X
YES
Set VSOUT_EN = 1
Set CLK_ON = 1
; T
Set OPM0 = 1
Bit check
Startup_Sig_proc
OK ?
NO
; T
YES
Startup_PLL
Sleep:
X
T
T
T
T
DCLK
Startup_PLL
Startup_Sig_Proc
Bit-check
Sleep
:
:
:
:
:
Defined by bits Sleep 0 to Sleep 4 in Control
Register 4
Defined by bit XSleep in Control register 4
Basic clock cycle
798.5
882
498
306
210
Is defined by the selected baud rate range and
T
Baud 0 and Baud 1 in Control Register 6.
Depends on the result of the bit check.
If the bit check is ok, T
number of bits to be checked (N
on the utilized data rate.
If the bit check fails, the average time period for
that check despends on the selected baud-rate
range and on T
defined by bit Baud 0 and Baud 1 in Control
Register 6.
If in FSK mode the datastream is interrupted the
FSK-Demodulator-PLL tends to lock out and is
further not able to lock in, even there is a valid
data stream available.
In this case the transceiver must be set back to
IDLE mode.
DCLK
T
T
T
T
.The baud-rate range is defined by bit
DCLK
DCLK
DCLK
DCLK
T
DCLK
(typ)
XDCLK
(BR_Range 0)
(BR_Range 1)
(BR_Range 2)
(BR_Range 3)
. The baud-rate range is
Bit-check
4689F–RKE–08/06
depends on the
Bit-check
) and