ATA5812-PLQW80 Atmel, ATA5812-PLQW80 Datasheet - Page 26

• Manufacturer Part Number: ATA5812-PLQW80
• Description: RF Transceiver RF Data Control Transceiver
• Manufacturer: Atmel

Specifications of ATA5812-PLQW80

• Wireless Frequency: 226 KHz
• Interface Type: 4-Wire SPI
• Noise Figure: 7 dB
• Output Power: 10 dBm
• Operating Supply Voltage: 2.4 V to 5.25 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-48
• Maximum Data Rate: 20 Kbps
• Minimum Operating Temperature: - 40 C
• Modulation: ASK, FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1
Figure 6-3.
6.2
26
Pin CLK
Basic Clock Cycle of the Digital Circuitry
ATA5811/ATA5812
(Control register 3)
Clock Timing
N_RESET
CLK_ON
VSOUT
CLK
The variable FREQ depends on FREQ2 and FREQ3, which are defined by the bits FR0 to FR8
in control register 2 and 3 and is calculated as follows:
FREQ = 3584 + FREQ2 + FREQ3
Only the range of FREQ = 3803 to 4053 of this register should be used because otherwise har-
monics of f
FREQ_max = 4053). The resulting tuning range is ±118 ppm at 868.3 MHz and more than
±150 ppm at 433.92 MHz or 315 MHz.
Pin CLK is an output to clock a connected microcontroller. The clock frequency f
as follows:
Because the enabling of pin CLK is asynchronous the first clock cycle may be incomplete. The
signal at CLK output has a nominal 50% duty cycle.
The complete timing of the digital circuitry is derived from one clock. According to
on page
a divider.
T
f
f
DCLK
DCLK
CLK
• Timing of the polling circuit including Bit-check
• TX bit rate
V
Thres_2
=
=
controls the following application relevant parameters:
f
---------- -
f
---------- -
XTO
25, this clock cycle T
= 2.38V (typically)
XTO
16
3
XTO
and f
V
Thres_2
CLK
= 2.38V (typically)
can cause interference with the received signals (FREQ_min = 3803,
DCLK
is derived from the crystal oscillator (XTO) in combination with
CLK
4689F–RKE–08/06
is calculated
Figure 6-2