N25Q128A13BF840E NUMONYX, N25Q128A13BF840E Datasheet - Page 37

• Manufacturer Part Number: N25Q128A13BF840E
• Description: 128MBQUAD IO,XIP VDFPN 8X6 3VT&R
• Manufacturer: NUMONYX

Table 3.
6.2.1
NVCR<5>
NVCR<4>
NVCR<3>
NVCR<2>
NVCR<1:0>
Bit
Non-Volatile Configuration Register
Dummy clock cycle NV configuration bits (NVCR bits from 15 to 12)
The bits from 15 to 12 of the Non Volatile Configuration register store the default settings for
the dummy clock cycles number after the fast read instructions (in all the 3 available
protocols). The dummy clock cycles number can be set from 1 up to 15 as described here,
according to operating frequency (the higher is the operating frequency, the bigger must be
the dummy clock cycle number) to optimize the fast read instructions performance.
The default values of these bits allow the memory to be safely used with fast read
instructions at the maximum frequency (108 MHz). Please note that if the dummy clock
number is not sufficient for the operating frequency, the memory reads wrong data.
Table 4.
1. All values are guaranteed by characterization and not 100% tested in production.
Dummy Clock
Fast POR x
READ
Reset/Hold
disable
Quad Input
Command
Dual Input
Command
Reserved
Parameter
10
1
2
3
4
5
6
7
8
9
Maximum allowed frequency (MHz)
111
0
1
0
1
0
1
0
1
xx
Value
FASTREAD
105
108
108
108
108
108
108
108
50
95
Maximum allowed frequency (MHz)
Enabled
Disabled (default)
disabled
enabled (default)
enabled
disabled (default)
enabled
disabled (default)
Don't care
Description
30 (default)
DOFR
105
108
108
108
108
108
108
50
85
95
POR phase < 100us only read available
POR phase ~ 700us all instructions
available
Disable Pad Hold/Reset functionality
Enable command on four input line
Enable command on two input line
Default value = "11"
DIOFR
105
108
108
108
108
39
59
75
88
94
(1)
QOFR
105
108
108
108
108
43
56
70
83
94
Note
QIOFR
105
108
20
39
49
59
69
78
86
95
37/180