N25Q128A13BF840E NUMONYX, N25Q128A13BF840E Datasheet - Page 13

• Manufacturer Part Number: N25Q128A13BF840E
• Description: 128MBQUAD IO,XIP VDFPN 8X6 3VT&R
• Manufacturer: NUMONYX

Note:
Table 1.
1. Provides dual and quad I/O for Extended SPI protocol instructions, dual I/O for Dual I/O SPI protocol instructions, and
2. Provides dual and quad instruction input for Extended SPI protocol, dual instruction input for Dual I/O SPI protocol, and
3. Provides quad I/O for Extended SPI protocol instructions, and quad I/O for Quad I/O SPI protocol instructions.
4. Reset functionality available with a dedicated part number. See
C
DQ0
DQ1
S
W/VPP/DQ2
HOLD/DQ3
V
V
CC
SS
quad I/O for Quad I/O SPI protocol instructions.
quad instruction input for Quad I/O SPI protocol.
Signal
(4)
The memory can be write protected by software using a mix of volatile and non-volatile
protection features, depending on the application needs. The protection granularity is of 64-
Kbyte (sector granularity) for volatile protections.
The N25Q128 has 64 one-time-programmable bytes (OTP bytes) that can be read and
programmed using two dedicated instructions, Read OTP (ROTP) and Program OTP
(POTP), respectively. These 64 bytes can be permanently locked by a particular Program
OTP (POTP) sequence. Once they have been locked, they become read-only and this state
cannot be reversed.
Many different N25Q128 configurations are available, please refer to the ordering scheme
page for the possibilities. Additional features are available as security options (The Security
features are described in a dedicated Application Note). Please contact your nearest
Numonyx Sales office for more information.
Figure 1.
Reset functionality is available in devices with a dedicated part number. See
Ordering
Signal names
Serial Clock
Serial Data input
Serial Data output
Chip Select
Write Protect/Enhanced Program supply voltage/additional data I/O
Hold (Reset function available upon customer request)/additional data I/O
Supply voltage
Ground
information.
Logic diagram
W/V
HOLD/DQ3
PP
/DQ2
DQ0
C
S
Description
Section 16: Ordering
V CC
V SS
Logic_Diagram_x25x
DQ1
information.
Section 16:
Input
I/O
I/O
Input
I/O
I/O
–
–
13/180
I/O
(1)
(2)
(3)
(3)