N25Q128A13BF840E NUMONYX, N25Q128A13BF840E Datasheet - Page 119

• Manufacturer Part Number: N25Q128A13BF840E
• Description: 128MBQUAD IO,XIP VDFPN 8X6 3VT&R
• Manufacturer: NUMONYX

N25Q128 - 3 V
Instructions
Figure 51. Subsector Erase instruction sequence DIO-SPI
S
0
1
2
3
4
5
6
7
8
9
10 11
12 13 14 15
C
Instruction
24-Bit Address
22 20 18 16
6
4
2
0
14 12 10
8
DQ0
7
5
3
1
23 21 19 17
15 13 11
9
DQ1
Dual_S ubsector_E rase
9.2.9
Sector Erase (SE)
The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code and the address on the two pins DQ0 and
DQ1, the instruction functionality is exactly the same as the Sector Erase (SE) instruction of
the Extended SPI protocol, please refer to
Section 9.1.18: Sector Erase (SE)
for further
details.
Figure 52. Sector Erase instruction sequence DIO-SPI
S
0
1
2
3
4
5
6
7
8
9 10 11
12 13 14 15
C
24-Bit Address
Instruction
22 20 18 16
6
4
2
0
14 12 10 8
DQ0
7
5
3
1
23 21 19 17
15 13 11 9
DQ1
Dual_Sector_Erase
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