AD7008JP50 Analog Devices Inc, AD7008JP50 Datasheet - Page 6

• Manufacturer Part Number: AD7008JP50
• Description: IC CMOS DDS MODULATOR 44-PLCC
• Manufacturer: Analog Devices Inc

Specifications of AD7008JP50

• Rohs Status: RoHS non-compliant
• Noise Floor: *
• Voltage - Supply: 5V
• Package / Case: 44-LCC

AD7008
CS (27)
D0-D15
(19-26, 8-15)
LOAD (36)
FSEL (31)
TC0-TC3
(32-35)
RESET (38)
CLOCK (30)
WR (16)
SLEEP (37)
SCLK (41)
SDATA (42)
CLK
D
PASS
D FLIP-FLOPS ARE MASTER SLAVE,
LATCHING DATA ON CLK RISING EDGE.
PASS FLIP-FLOPS ARE TRANSPARENT
WHEN THE CLOCK IS LOW.
CLK
TRANSFER CONTROL (TC) REGISTER
x 6
15:0 23:8
15:8 7:0
23:0
Q
CLK
7:0
RESET SYNCHRONIZATION
D Q
x 32
D Q
D Q
x 6
REGISTER
CONTROL
AD7008
LOGIC
1
0
x 24
AND
ASSEMBLY REGISTER
ASSEMBLY REGISTER
D Q
x 6
31:8
D Q
32-BIT PARALLEL
32-BIT SERIAL
ACCUM RESET
SLEEP
32
AM ENABLE
12
D Q
20
x 32
D Q
x 6
14 PIPELINE DELAYS
D Q
Figure 7. AD7008 CMOS DDS Modulator (See Table I)
ACCUMULATOR
D Q
x 6
PHASE
32
Figure 8. AD7008 Register and Control Logic
1
0
x 6
12
6
13 PIPELINE DELAYS
REGISTER
MUX
31:0
31:0
SUMMATION
CLK
5
TC2
LOAD
TC3
TC2
TC3
TC0
TC1
PHASE
D Q
–6–
0
x 32
1
TRANSFER DECODE
S
E
12
0
1
2
3
0
1
2
3
4
ROM
COS
SIN
CLK
x 5
CLK
CLK
FSELECT
10
10
3:0
D Q
D Q
x 5
CLK
11 PIPELINE DELAYS
9:0 19:10
SUMMATION
D Q
D Q
x 4
SIN/ COS
4
0
1
2
3
COMMAND REGISTER
10
10
D2
D1
D0
D3
SYNCHRO LOGIC
BUS MODE
32
12
10
32
CLK
CLK
PHASE REGISTER
IQ MOD REGISTER
10
IOUT/IOUT
CLK
CLK
FREQUENCY
DAC
REGISTERS
FREQ 1
FREQ 0
D Q
x 32
D Q
x 32
D Q
E
D Q
x 20
E
x 12
CLK
CLK
E
E
D Q
D Q
1
0
x32
ACCUMULATOR
RESET
TO PHASE
ACCUMULATOR
TO PHASE
SUMMATION
TO SIN/COS
SUMMATION
SLEEP
AM ENABLE
REV. B