AD7008JP50 Analog Devices Inc, AD7008JP50 Datasheet - Page 3

• Manufacturer Part Number: AD7008JP50
• Description: IC CMOS DDS MODULATOR 44-PLCC
• Manufacturer: Analog Devices Inc

Specifications of AD7008JP50

• Rohs Status: RoHS non-compliant
• Noise Floor: *
• Voltage - Supply: 5V
• Package / Case: 44-LCC

REV. B
TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTE
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
May be reduced to 1t
FSEL, LOAD,
TC3–TC0
CLOCK
Figure 1. Clock Synchronization Timing
TC0–TC3
Figure 2. Register Transfer Timing
LOAD
50
20
20
5
3
4t
2t
5
5
10
10
20
10
3
3
20
8
8
10
10
1
Min
if LOAD is synchronized to CLOCK and Setup (t
1
1
t
VALID
4
AD7008AP20
t
5
t
Typ
8
t
2
VALID
t
7
Max
t
1
t
6
(V
t
9
AA
t
3
= V
Min
20
8
8
5
3
4t
2t
5
5
10
10
20
10
3
3
20
8
8
10
10
VALID
DD
1
1
+5 V
AD7008JP50
Typ
5%; T
4
) and Hold (t
A
–3–
= T
Max
MIN
D0–D15
5
to T
) Times for LOAD to CLOCK are observed.
WR
CS
SDATA
SCLK
MAX
, unless otherwise noted)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 3. Parallel Port Timing
Figure 4. Serial Port Timing
t
19
DB31
Test Conditions/Comments
CLOCK Period
CLOCK High Duration
CLOCK Low Duration
CLOCK to Control Setup Time
CLOCK to Control Hold Time
LOAD Period
LOAD High Duration
LOAD High to TC0–TC3 Setup Time
LOAD High to TC0–TC3 Hold Time
WR Falling to CS Low Setup Time
WR Falling to CS Low Hold Time
Minimum WR Low Duration
Minimum WR High Duration
WR to D0–D15 Setup Time
WR to D0–D15 Hold Time
SCLK Period
SCLK High Duration
SCLK Low Duration
SCLK Rising to SDATA Setup Time
SCLK Rising to SDATA Hold Time
t
20
t
t
10
14
VALID DATA
t
t
15
11
t
12
t
18
DB0
t
16
1
t
13
AD7008
t
17