AD7008JP50 Analog Devices Inc, AD7008JP50 Datasheet - Page 10

• Manufacturer Part Number: AD7008JP50
• Description: IC CMOS DDS MODULATOR 44-PLCC
• Manufacturer: Analog Devices Inc

Specifications of AD7008JP50

• Rohs Status: RoHS non-compliant
• Noise Floor: *
• Voltage - Supply: 5V
• Package / Case: 44-LCC

AD7008
Parallel Configuration
The AD7008 functions fully in the parallel mode. There are
two parallel modes of operation. Both are similar but are tai-
lored for different bus widths, 8 and 16 bits. All modes of op-
eration can be controlled by the parallel interface.
On power up and reset, the chip must be configured by instruc-
ting the command register how to operate. The command reg-
ister may be used to set the device up for 8- or 16-bit mode,
Figure 12. Parallel Interface to a 16- or 32-Bit DSP or
Microprocessor
DMA02
DMA01
DMA00
DMWR
DMS1
DMDXX–DATA BITS
DMAXX–ADDRESS BITS
+5V
(ANTENNA)
10 BITS
6
4
5
INPUT
3
2
1
14
V
V
+5V
7
CC
EE
OUT
G1
G2A
G2B
RF
C
B
A
74HC138
U2
50MHz
5
K1115
AD7008
U1
8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
5
10
11
12
13
14
15
7
9
RESET
AD607
R
390
SET
DMD36
DMD37
DMD38
DMD39
FILTER
DMD24
DMD25
DMD26
DMD27
DMD28
DMD29
DMD30
DMD31
DMD32
DMD33
DMD34
DMD35
DMD36
DMD37
DMD38
DMD39
GND
–16dBm
0.1µF
19
20
21
22
23
24
25
26
10
11
12
13
14
15
16
GENERATOR
27
32
33
34
35
36
41
42
31
30
38
37
8
9
MIDPOINT
CIRCUIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
WR
CS
TC0
TC1
TC2
TC3
LOAD
SCLK
SDATA
FSELECT
CLK
RESET
SLEEP
BIAS
BIAS
AD7008
Figure 13. AD7008 and AD607 Receiver Circuit
U3
4.7
µF
330
FSADJUST
BANDPASS
AGND
DGND
DGND
DGND
DGND
COMP
FILTER
TEST
V
IOUT
IOUT
V
V
V
V
REF
AA
DD
DD
DD
100
nF
AGC VOLTAGE
330
3
17
28
39
44
7
18
29
43
40
2
1
4
6
5
0.1µF
C1
49.9
R4
+5V
+5V
+5V
+5V
49.9
100
R5
390
R3
nF
0.1µF
C2
+5V
+5V
–10–
10
sleep mode, amplitude control and synchronization logic. At
reset, the chip defaults to 8-bit bus, no amplitude control and
logic synchronized. The code fragment below indicates how
the initialization code for the AD7008 might look using the
ADSP-21020.
Local Oscillator
The AD7008 is well suited for applications such as local oscilla-
tors used in super-heterodyne receivers. Although the AD7008
can be used in a variety of receiver designs, one simple local os-
{dds_para is a port define to decode for
the parallel assembly register write pulse.
dds_cont is a port defined to decode for
the TC control Load pin.
ister must first be loaded with configura-
tion information. In this example, the chip
is set up for 16 bits data. See Table III
for details.}
r4 = 0x00010000; {16 bits, Normal Op., AM
dm(dds_para) = r4; {write data to parallel
r4 = 0x00000000;
dm(dds_cont) = r5; {No data written, data is
r4 = 0x051E0000; {1 MHz=051EB852, load high
dm(dds_para) = r4;
r4 = 0xB8520000; {Now load low word}
dm(dds_para)=r4;
r4 = 0x80000000; {Transfer data from the
dm(dds_cont)=r4;
VOLTAGE
PTAT
10
VMID
DETECTOR
AGC
OPTIONAL
OR LPF
BPF
disabled, Synchronizer
enabled}
assembly register}
just transferred from
parallel assembly
register to the command
register}
word first}
parallel assembly
register to Freq0}
PLL
0
90
The Command reg-
PLL INPUT
FM OUTPUT
AM OUTPUT
RECEIVED
SIGNAL
STRENGTH
INDICATOR
REV. B