CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 66

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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14.1.1
The PxALT registers control whether the port pins are used
for general-purpose I/O or for their alternate function. Each
port pin can be controlled independently.
A clear bit in the alternate function register causes the cor-
responding pin to be used for general-purpose I/O. In this
configuration, the output buffer is controlled by the direction
register (PxDIR) and the data output register (PxDOUT).
The input buffer is visible to software as the data input reg-
ister (PxDIN).
A set bit in the alternate function register (PxALT) causes
the corresponding pin to be used for its peripheral I/O func-
tion. When the alternate function is selected, the output
buffer data and TRI-STATE configuration are controlled by
signals from the on-chip peripheral device.
A reset operation clears the port alternate function regis-
ters, which initializes the pins as general-purpose I/O ports.
This register must be enabled before the corresponding al-
ternate function is enabled.
PxALT
14.1.2
The port direction register (PxDIR) determines whether
each port pin is used for input or for output. A clear bit in this
register causes the corresponding pin to operate as an in-
put, which puts the output buffer in the high-impedance
state. A set bit causes the pin to operate as an output, which
enables the output buffer.
A reset operation clears the port direction registers, which
initializes the pins as inputs.
PxDIR
7
7
Port Alternate Function Register (PxALT)
Port Direction Register (PxDIR)
The PxALT bits control whether the corre-
sponding port pins are general-purpose I/O
ports or are used for their alternate function by
an on-chip peripheral.
0
1
The PxDIR bits select the direction of the cor-
responding port pin.
0
1
–
–
–
–
General-purpose I/O selected.
Alternate function selected.
Input.
Output.
PxALT
PxDIR
0
0
66
14.1.3
The data input register (PxDIN) is a read-only register that
returns the current state on each port pin. The CPU can
read this register at any time even when the pin is config-
ured as an output.
PxDIN
14.1.4
The data output register (PxDOUT) holds the data to be
driven on output port pins. In this configuration, writing to
the register changes the output value. Reading the register
returns the last value written to the register.
A reset operation leaves the register contents unchanged.
At power-up, the PxDOUT registers contain unknown val-
ues.
PxDOUT
14.1.5
The weak pull-up register (PxWPU) determines whether the
port pins have a weak pull-up on the output buffer. The pull-
up device, if enabled by the register bit, operates in the gen-
eral-purpose I/O mode whenever the port output buffer is
disabled. In the alternate function mode, the pull-ups are al-
ways disabled.
A reset operation clears the port weak pull-up registers,
which disables all pull-ups.
PxWPU
7
7
7
Port Data Input Register (PxDIN)
Port Data Output Register (PxDOUT)
Port Weak Pull-Up Register (PxWPU)
The PxDIN bits indicate the state on the cor-
responding port pin.
0
1
The PxDOUT bits hold the data to be driven
on pins configured as outputs in general-pur-
pose I/O mode.
0
1
The PxWPU bits control whether the weak
pull-up is enabled.
0
1
–
–
–
–
–
–
Pin is low.
Pin is high.
Drive the pin low.
Drive the pin high.
Weak pull-up disabled.
Weak pull-up enabled.
PxDOUT
PxWPU
PxDIN
0
0
0