CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 102

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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17.6.6
The audio interface provides a FREEZE input, which allows
to freeze the status of the audio interface while a develop-
ment system examines the contents of the FIFOs and reg-
isters.
When the FREEZE input is asserted, the audio interface be-
haves as follows:
The time at which these registers are frozen will vary be-
cause they operate from a different clock than the one used
to generate the freeze signal.
The receive FIFO or receive DMA registers are not up-
dated with new data.
The receive status bits (RXO, RXE, RXF, and RXAF) are
not changed, even though the receive FIFO or receive
DMA registers are read.
The transmit shift register (ATSR) is not updated with
new data from the transmit FIFO or transmit DMA regis-
ters.
The transmit status bits (TXU, TXF, TXE, and TXAE) are
not changed, even though the transmit FIFO or transmit
DMA registers are written.
Freeze Mode
102
17.7
ADMACR
ARSCR
ARDR0
ARDR1
ARDR2
ARDR3
ATSCR
ATDR0
ATDR1
ATDR2
ATDR3
AISCR
AGCR
Name
ARFR
ACCR
ATFR
AUDIO INTERFACE REGISTERS
Table 42 Audio Interface Registers
FF FD4Ch
FF FD5Ch
FF FD40h
FF FD42h
FF FD44h
FF FD46h
FF FD48h
FF FD4Ah
FF FD4Eh
FF FD50h
FF FD52h
FF FD54h
FF FD56h
FF FD58h
FF FD5Ah
FF FD5Eh
Address
Configuration Register
Audio Interrupt Status
Audio Transmit Status
Audio Receive Status
and Control Register
and Control Register
and Control Register
Audio Transmit FIFO
Audio Transmit DMA
Audio Transmit DMA
Audio Transmit DMA
Audio Transmit DMA
Audio Receive FIFO
Audio Receive DMA
Audio Receive DMA
Audio Receive DMA
Audio Receive DMA
Audio Clock Control
Audio DMA Control
Audio Global
Description
Register 0
Register 1
Register 2
Register 3
Register 0
Register 1
Register 2
Register 3
Register
Register
Register
Register