CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 125

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

20.1.1
The Microwire interface is a full duplex transmitter/receiver.
A 16-bit shifter, which can be split into a low and high byte,
is used for both transmitting and receiving. In 8-bit mode,
only the lower 8-bits are used to transfer data. The transmit-
ted data is shifted out through MDODI pin (master mode) or
MDIDO pin (slave mode), starting with the most significant
bit. At the same time, the received data is shifted in through
MDIDO pin (master mode) or MDODI pin (slave mode), also
starting with the most significant bit first.
The shift in and shift out are controlled by the MSK clock. In
each clock cycle of MSK, one bit of data is transmitted/re-
ceived. The 16-bit shifter is accessible as the MWDAT reg-
ister. Reading the MWDAT register returns the value in the
read buffer. Writing to the MWDAT register updates the 16-
bit shifter.
20.1.2
The enhanced Microwire interface implements a double
buffer on read. As illustrated in Figure 48, the double read
buffer consists of the 16-bit shifter and a buffer, called the
read buffer.
The 16-bit shifter loads the read buffer with new data when
the data transfer sequence is completed and previous data
in the read buffer has been read. In master mode, an Over-
run error occurs when the read buffer is full, the 16-bit shifter
is full and a new data transfer sequence starts.
When 8-bit mode is selected, the lower byte of the shift reg-
ister is loaded into the lower byte of the read buffer and the
read buffer’s higher byte remains unchanged.
Shifting
Reading
Interrupt
Request
System
Clock
Write
Write
Data
Data
Clock Prescaler + Select
Figure 48. Microwire Block Diagram
16-BIt Shift Register
Data In
MSK
16-BIt Read Buffer
8
8
Control + Status
MWDAT
125
Data Out
The “Receive Buffer Full” (RBF) bit indicates if the MWDAT
register holds valid data. The OVR bit indicates that an over-
run condition has occurred.
20.1.3
The “Microwire Busy” (BSY) bit indicates whether the MW-
DAT register can be written. All write operations to the MW-
DAT register update the shifter while the data contained in the
read buffer is not affected. Undefined results will occur if the
MWDAT register is written to while the BSY bit is set.
20.1.4
Two clocking modes are supported: the normal mode and
the alternate mode.
In the normal mode, the output data, which is transmitted on
the MDODI pin (master mode) or the MDIDO pin (slave
mode), is clocked out on the falling edge of the shift clock
MSK. The input data, which is received via the MDIDO pin
(master mode) or the MDODI pin (slave mode), is sampled
on the rising edge of MSK.
In the alternate mode, the output data is shifted out on the
rising edge of MSK on the MDODI pin (master mode) or
MDIDO pin (slave mode). The input data, which is received
via MDIDO pin (master mode) or MDODI pin (slave mode),
is sampled on the falling edge of MSK.
The clocking modes are selected with the MSKM bit. The
SCIDL bit allows selection of the value of MSK when it is idle
(when there is no data being transferred). Various MSK
clock frequencies can be programmed via the MCDV bits.
Figures 27, 28, 29, and 30 show the data transfer timing for
Writing
Clocking Modes
Master
Slave
Master
Slave
Master
DS068
MDODI
MDIDO
MSK
MWCS
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