CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 190

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

www.national.com
27.9
Symbol Figure
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MDOnf
MDOh
MSKh
MSKp
MSKh
MCSh
MCSs
MSKh
MSKp
MSKd
MSKs
MDOf
MSKl
MDIh
MSKl
MDIs
MICROWIRE/SPI TIMING
81
81
81
82
81
81
81
82
81
82
81
83
81
83
81
83
81
81
81
82
81
81
81
82
85
Microwire Clock High
Microwire Clock Low
Microwire Clock Period
MSK Hold (slave only)
MSK Setup (slave only)
MWCS Hold (slave only)
MWCS Setup (slave only)
Microwire Data In Hold (master)
Microwire Data In Hold (slave)
Microwire Data In Setup
Microwire Clock High
Microwire Clock Low
Microwire Clock Period
MSK Leading Edge Delayed (master
only)
Microwire Data Float
(slave only)
Microwire Data Out Hold
Microwire Data No Float (slave only)
Description
b
Table 61 Microwire/SPI Signals
Microwire/SPI Output Signals
Microwire/SPI Input Signals
At 2.0V (both edges)
At 0.8V (both edges)
SCIDL bit = 0; Rising Edge
(RE) MSK to next RE MSK
SCIDL bit = 1; Falling Edge
(FE) MSK to next FE MSK
After MWCS goes inactive
Before MWCS goes active
SCIDL bit = 0; After FE
MSK
SCIDL bit = 1; After RE
MSK
SCIDL bit = 0; Before RE
MSK
SCIDL bit = 1; Before FE
MSK
Normal Mode; After RE
MSK
Alternate Mode; After FE
MSK
Normal Mode; After RE
MSK
Alternate Mode; After FE
MSK
Normal Mode; Before RE
MSK
Alternate Mode; Before FE
MSK
At 2.0V (both edges)
At 0.8V (both edges)
SCIDL bit = 0: Rising Edge
(RE) MSK to next RE MSK
SCIDL bit = 1: Falling Edge
(FE) MSK to next FE MSK
Data Out Bit #7 Valid
After RE on MCSn
Normal Mode; After FE
MSK
Alternate Mode; After RE
MSK
After FE on MWCS
190
Reference
Min (ns)
0.5 t
200
100
0.0
80
80
40
80
40
80
40
80
40
40
0
0
-
MSK
Max (ns)
1.5 t
25
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MSK