CY7C0851AV-133AXI Cypress Semiconductor Corp, CY7C0851AV-133AXI Datasheet - Page 34

• Manufacturer Part Number: CY7C0851AV-133AXI
• Description: CY7C0851AV-133AXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0851AV-133AXI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 2M (64K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document History Page
Document #: 38-06070 Rev. *J
Document Title: CY7C0850AV, CY7C0851V/CY7C0851AV, CY7C0852V/CY7C0852AV, CY7C0853V/CY7C0853AV,
FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
Document Number: 38-06070
REV.
*C
*D
*G
*H
*A
*B
*E
*F
**
*I
ECN NO.
2544945
2897087
127809
210948
216190
231996
238938
329122
389877
391597
sion Date
See ECN
See ECN
See ECN
See ECN
See ECN
See ECN
See ECN
Submis-
08/04/03
07/29/08
03/22/10
VKN/AESA Updated Template. Updated ordering information
YDT/Dcon Corrected Revision of Document. CMS does not reflect this rev change
Change
Orig. of
RAME
WWZ
SPN
SPN
KGH
SPN
YDT
YDT
Description of Change
This data sheet has been extracted from another data sheet: the 2M/4M/9M
data sheet. The following changes have been made from the original as
pertains to this device:
Updated capacitance values
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Corrected 0853 pins L3 and L12
Added discussion of Pause/Restart for JTAG boundary scan
Power up requirements added to Maximum Ratings information
Revise t
Updated I
Updated t
Separated out from the 4M data sheet
Added 133-MHz Industrial device to Ordering Information table
Changed mailbox addresses from 1FFFE and 1FFFF to 3FFFE and 3FFFF.
Removed “A particular port can write to a certain location while another port is
reading that location.” from Functional Description.
Merged 0853 (9Mx36) with 0852 (4Mx36) and 0851(2Mx36), add 0850 (1M x36),
to the data sheet.
Added product selection table.
Added JTAG ID code for 1M device.
Added note 14.
Updated boundary scan section.
Updated function description for the merge and addition.
Updated Marketing part numbers
Updated Read-to-Write-to-Read timing diagram to reflect accurate bus
turnaround scheme.
Added I
Changed t
Changed t
Added figure Disabled-to-Read-to-Read-to-Read-to-Write
Added figure Disabled-to-Write-to-Read-to-Write-to-Read
Added figure Disabled-to-Read-to-Disabled-to-Write
Added figure Read-to-Readback-to-Read-to-Read (R/W = HIGH)
Updated Read-to-Write-to-Read timing diagram to correct the data out schemes
Updated Disabled-to-Read-to-Read-to-Read-to-Write timing diagram to correct
the chip enable, data in, and data out schemes
Updated Disabled-to-Write-to-Read-to-Write-to-Read timing diagram to correct
the chip enable and output enable schemes
Updated Disabled-to-Read-to-Disabled-to-Write timing diagram to correct the
chip enable and output enable schemes
Updated counter reset section to reflect mirror register behavior
Removed obsolete parts from ordering information table
Updated package diagrams
SB5
cd2
cc
HA
RSCNTINT
RSF
, t
numbers
, t
OE
HB
CY7C0850AV,CY7C0851V/CY7C0851AV
to 10ns
, t
, t
OHZ
HD
to 10ns
, t
for -100 speed
CKHZ
, t
CKLZ
for the CY7C0853V to 4.7 ns
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Page 34 of 36
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