CY7C0851AV-133AXI Cypress Semiconductor Corp, CY7C0851AV-133AXI Datasheet
CY7C0851AV-133AXI
Specifications of CY7C0851AV-133AXI
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CY7C0851AV-133AXI Summary of contents
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... JTAG for boundary scan, and asynchronous Master Reset (MRST). The CY7C0853V/CY7C0853AV device in this family has limited features. Please see Operations” on page 9. 1-Mbit 2-Mbit (32K x 36) (64K x 36) CY7C0850AV CY7C0851V/ CY7C0851AV 167 167 4.0 4.0 225 225 176TQFP 176TQFP 172FBGA 172FBGA • ...
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... Mirror Reg CLK L CNTINT L Interrupt INT L Logic Note 1. 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV I/O I/O Control Control True Dual-Ported RAM Array Address Address Decode Decode ...
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... Counter Interrupt ....................................................... 10 Retransmit ................................................................. 10 Mask Reset Operation ............................................... 10 Mask Load Operation ................................................ 10 Mask Readback Operation ........................................ 10 Counting by Two ....................................................... 10 IEEE 1149.1 Serial Boundary Scan (JTAG) ................... 13 Performing a TAP Reset ........................................... 13 Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Maximum Ratings ........................................................... 14 Operating Range ............................................................. 14 Electrical Characteristics ............................................... 14 Capacitance .................................................................... 14 Switching Characteristics 1.............................................. 5 JTAG Timing ................................................................... 17 Ordering Information ...
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... A16L A14L DQ22L DQ18L N DQ24L DQ20L DQ8L DQ6L P DQ23L DQ21L TDO VSS Note 2. For CY7C0851V/CY7C0851AV, pins M1 and M14 are NC. For CY7C0850AV, pins K3, K12 M1, and M14 are NC Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV Figure 1. 172-Ball BGA (Top View DQ13L VDD DQ11L DQ11R VDD DQ14L ...
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... A10L VSS K A11L A12L A15L L VDD A13L VSS M A16L A14L DQ22L N DQ24L DQ20L DQ8L P DQ23L DQ21L TDO Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV Figure 2. 172-Ball BGA (Top View VSS DQ13L VDD DQ11L DQ11R VDD DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ27L INTL DQ15L ...
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... A 12L 13L 40 A 14L [ 15L [ 16L 43 DQ 24L 44 DQ 20L Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV CY7C0850AV CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV DQ 132 34R DQ 131 35R NC 130 A 129 0R A 128 1R A 127 2R A 126 3R V 125 SS V 124 DD A 123 4R A 122 5R A ...
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... Power inputs. DD Notes 3. 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits 4. These pins are not available for CY7C0853V/CY7C0853AV device. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Description . MAX is asserted LOW when the right ...
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... OE is “Don’t Care” for mailbox operation least one of B0, B1, B2 must be LOW. 9. A16x for CY7C0851V/CY7C0851AV, therefore the Interrupt Addresses are FFFF and EFFF; A16x and A15x are NC for CY7C0850AV, therefore the Interrupt Addresses are 7FFF and 6FFF. 10. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW. ...
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... A Mask Reset followed by a Counter Reset Notes 12. This section describes the CY7C0852V/CY7C0852AV, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0851V/CY7C0851AV has 16 address bits, register lengths of 16 bits, and a maximum address value of FFFF. The CY7C0850AV has 15 address bits, register lengths of 15 bits, and a maximum address value of 7FFF ...
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... The mask register is reset to all “1s,” which unmasks every bit of the counter. Master reset (MRST) also resets the mask register to all “1s.” Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Mask Load Operation The mask register is loaded with the address value presented at the address lines ...
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... Lines From 17 Mask Register 17 From Mask 17 From Counter Note 14. 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV Mask Register Counter/ Address Register Load/Increment Mirror Counter Increment Logic ...
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... Address Counter = 8 Max Address Register Max + 1 Address Register Notes 15. 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits 16. The “X” in this diagram represents the counter upper bits Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV ...
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... Places the BYR between TDI and TDO. Loads the IDR with the vendor ID code and places the register between TDI and TDO. Places BYR between TDI and TDO. Forces all CY7C0851AV/CY7C0852AV/ CY7C0853AV output drivers to a High-Z state. Controls boundary to 1/0. Places BYR between TDI and TDO. ...
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... Operating current SB5 (V = Max mA OUT Outputs disabled Capacitance [21] Part Number Parameter CY7C0850AV,CY7C0851V C IN CY7C0851AV, CY7C0852V, C OUT CY7C0852AV CY7C0853V,CY7C0853AV OUT Notes 19. The voltage on any input or I/O pin can not exceed the power pin during power up. 20. Pulse width < 20 ns. 21. C also references C . ...
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... CNTRST hold time HRST t CNT/MSK setup time SCM t CNT/MSK hold time HCM Note 23. Except JTAG signals (t and t < [max.]). r f Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV Figure 6. AC Test Load and Waveforms OUTPUT (b) Three-state Delay (Load 2) 3.0 V 90% 10 < -167 CY7C0850AV ...
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... Master reset to outputs inactive RSF t Master reset to counter interrupt flag RSCNTINT reset time Notes 24. This parameter is guaranteed by design, but it is not production tested. 25. Test conditions used are Load 2. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV -167 -133 CY7C0850AV CY7C0850AV CY7C0853V CY7C0851V/AV CY7C0851V/AV ...
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... TDI hold after TCK clock rise TDIH t TCK clock LOW to TDO valid TDOV t TCK clock LOW to TDO invalid TDOX Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV Description Figure 7. JTAG Switching Waveform TMSS t TMSH t TDIS t TDIH t ...
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... OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge. 28. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH. 29. The output is disabled (high-impedance state 30. Addresses do not have to be accessed sequentially since ADS = CNTEN = V Numbers are for reference only. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV Figure 8. Master Reset t RSR ACTIVE [26, 27, 28, 29, 30] Figure 9 ...
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... DATA IN DATA OUT Notes 31. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV device from this data sheet. ADDRESS = ADDRESS (B1) 32. ADS = CNTEN= B0 – LOW; MRST = CNTRST = CNT/MSK = HIGH. 33. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. ...
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... B0 – R/W = LOW CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed 0 1 (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV ...
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... B0 – R/W = LOW CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed 0 1 (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV A n ...
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... Figure 16. Disabled to Write- to- Read to Write-to-Read t CYC2 t CL2 CLK R ADDRESS DATA D IN DATA OUT DISABLED Figure 17. Disabled-to-Read to Disabled-to-Write t CYC2 t CL2 CLK R ADDRESS DATA IN DATA OUT DISABLED Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV t CH2 n n+2 WRITE READ WRITE t CH2 n+1 n OHZ n+2 t CD2 Q n READ DISABLED WRITE ...
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... Figure 18. Read-to-Readback to Read-to-Read (R/W = HIGH) t CYC2 t t CL2 CH2 CLK t SAD ADS CNTEN t t SCN HCN ADDRESS COUNTER A INTERNAL n ADDRESS OE DATA OUT INCREMENT Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV t HAD A A n+1 Q n+1 NO OPERATION READ READ READBACK INCREMENT CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV n n+2 n+3 n+4 Q ...
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... B0 – LOW MRST = CNT/MSK = HIGH 43. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. 44. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV [42, 43, 44] Figure 19. Counter Reset CD2 ...
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... Address in output mode. Host must not be driving address bus after t 47. Address in input mode. Host can drive address bus after t 48 the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CA2 ...
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... This timing is valid when one port is writing, and other port is reading the same location at the same time 51 < minimum specified value, then R_Port is Read the most recent data (written by L_Port) only ( CCS > minimum specified value, then R_Port is Read the most recent data (written by L_Port) (t Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV ...
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... – LOW R/W = CNTRST = MRST = HIGH 54. CNTINT is always driven. 55. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 56. The mask register assumed to have the value of 1FFFFh. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [52, 53, 54, 55, 56] 1FFFE 1FFFF Last_Loaded t ...
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... When CE changes state, deselection and Read happen after one cycle of latency. 64 device has 18 address bits, 4M device has 17 address bits device has 16 address bits, and 1M device has 15 address bits. 65. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV [57, 58, 59, 60, 61 ...
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... Ordering Code (MHz) Diagram 167 CY7C0851V-167BBC 51-85114 172-Ball Grid Array ( 1.25 mm) with 1 mm pitch CY7C0851AV-167BBXC 133 CY7C0851AV-133AXI 51-85132 176-Pin Thin Quad Flat Pack ( 1.4 mm) (Pb-free) CY7C0851AV-133BBI Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV http://www.cypress.com/products or contact your local sales representative. Package Type 172-Ball Grid Array ( 1.25 mm) with 1 mm pitch (Pb-free) ...
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... Ordering Code Definition 085 X Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV X XXX CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Operating Range C = Com m ercial I = Industrial free (RoHS Com pliant) Package: A=TQFP; BB=FBGA Speed in M Hz: 100/133/167 V/AV:3.3 V Depth:1=64K; 2=128K; 3=256K 0 = DP, 8=Synchronous, 5=width :x36 7 = Dual Port SRAM Com pany ID Cypress Page ...
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... Package Diagrams Figure 24. 172-Ball FBGA ( 1.25 mm) (51-85114) Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV 51-85114 *C Page [+] Feedback ...
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... Package Diagrams Figure 25. 176-Pin Thin Quad Flat Pack (24 × 24 × 1.4 mm) (51-85132) Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV 51-85132 *A Page [+] Feedback ...
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... Joint Test Action Group SRAM static random access memory TCK test clock input TDI test data input TDO test data output TQFP thin quad plastic flatpack Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA ...
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... Document History Page Document Title: CY7C0850AV, CY7C0851V/CY7C0851AV, CY7C0852V/CY7C0852AV, CY7C0853V/CY7C0853AV, FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM Document Number: 38-06070 Submis- Orig. of REV. ECN NO. sion Date Change ** 127809 08/04/03 *A 210948 See ECN *B 216190 See ECN YDT/Dcon Corrected Revision of Document. CMS does not reflect this rev change ...
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... REV. ECN NO. sion Date Change *J 3093275 11/23/2010 Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV Description of Change ADMU Added new part CY7C0851AV-133BBI in the ordering information table Added information for parts CY7C0851V/CY7C0852V/CY7C0853V Updated as per new template Added Contents page Added Acronyms and Units of Measure Added Ordering Code Definition ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06070 Rev. *J All products and company names mentioned in this document may be the trademarks of their respective holders. CY7C0850AV,CY7C0851V/CY7C0851AV cypress.com/go/plc Revised November 23, 2010 CY7C0852V/CY7C0852AV ...