CS42888-CQZ Cirrus Logic Inc, CS42888-CQZ Datasheet - Page 49

• Manufacturer Part Number: CS42888-CQZ
• Description: IC,Soundcard Circuits,CMOS,QFP,64PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42888-CQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 4 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• No. Of Adcs: 2
• No. Of Dacs: 4
• No. Of Input Channels: 8
• No. Of Output Channels: 4
• Adc / Dac Resolution: 24bit
• Ic Interface Type: Serial
• Supply Voltage Range: 3.14V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1183

DS717F2
6.12
6.12.1 Invert Signal Polarity (INV_AINX)
6.13
6.13.1 Interrupt Pin Control (INT[1:0])
6.14
6.14.1 DAC CLOCK ERROR (DAC_CLK ERROR)
Reserved
Reserved
Reserved
7
7
7
ADC Channel Invert (Address 17h)
Status Control (Address 18h)
Status (Address 19h) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated
mask register will always be “0” in this register.
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
Default = 00
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
Function:
Determines how the Interrupt pin (INT) will indicate an interrupt condition.
For DAC and ADC clock errors, the INT pin is set to “Level Active Mode” and will become active during
the clock error. For the ADCx_OVFL error, the INT pin is set to Level Active Mode and will become active
during the overflow error.
Default = x
Function:
Indicates an invalid MCLK to DAC_LRCK ratio. This status flag is set to “Level Active Mode” and becomes
active during the error condition. See
Reserved
Reserved
Reserved
6
6
6
Reserved
Reserved
Reserved
5
5
5
DAC_CLK Error
Reserved
Reserved
4
“System Clocking” on page 29
4
4
ADC_CLK Error
INV_AIN4
INT1
3
3
3
Reserved
INV_AIN3
INT0
2
2
2
for valid clock ratios.
ADC2_OVFL
INV_AIN2
Reserved
1
1
1
CS42888
ADC1_OVFL
INV_AIN1
Reserved
0
0
0
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