CS42888-CQZ Cirrus Logic Inc, CS42888-CQZ Datasheet - Page 42

IC,Soundcard Circuits,CMOS,QFP,64PIN,PLASTIC

CS42888-CQZ

Manufacturer Part Number
CS42888-CQZ
Description
IC,Soundcard Circuits,CMOS,QFP,64PIN,PLASTIC
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet

Specifications of CS42888-CQZ

Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
4 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
105 / 108 (Differential), 102 / 105 (Single-Ended)
Voltage - Supply, Analog
3.14 V ~ 5.25 V
Voltage - Supply, Digital
3.14 V ~ 5.25 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
No. Of Adcs
2
No. Of Dacs
4
No. Of Input Channels
8
No. Of Output Channels
4
Adc / Dac Resolution
24bit
Ic Interface Type
Serial
Supply Voltage Range
3.14V To 5.25V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1183

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS42888-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS42888-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
42
6.4
6.4.1
6.4.2
6.4.3
DAC_FM1
7
Functional Mode (Address 03h)
DAC Functional Mode (DAC_FM[1:0])
Default = 11
Master Mode
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
Slave Mode
11 - (Auto-detect sample rates)
Function:
Selects the required range of sample rates for the DAC serial port.
ADC Functional Mode (ADC_FM[1:0])
Default = 11
Master Mode
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
Slave Mode
11 - (Auto-detect sample rates)
Function:
Selects the required range of sample rates for the ADC serial port.
MCLK Frequency (MFREQ[2:0])
Default = 000
Function:
Sets the appropriate frequency for the supplied MCLK. For TDM and OLM #2 operation, ADC/DAC_SCLK
must equal 256Fs. For OLM #1 operation, ADC/DAC_SCLK must equal 128Fs. MCLK can be equal to or
greater than the higher frequency of ADC_SCLK or DAC_SCLK.
MFreq2
0
0
0
0
1
Table 10. MCLK Frequency Settings for I²S, Left and Right Justified Interface Formats
DAC_FM0
6
MFreq1
0
0
1
1
X
ADC_FM1
5
MFreq0
X
0
1
0
1
ADC_FM0
1.0290 MHz to 12.8000 MHz
1.5360 MHz to 19.2000 MHz
2.0480 MHz to 25.6000 MHz
3.0720 MHz to 38.4000 MHz
4.0960 MHz to 51.2000 MHz
4
Description
MFreq2
3
MFreq1
2
SSM
1024
256
384
512
768
MFreq0
Ratio (xFs)
1
DSM
128
192
256
384
512
CS42888
Reserved
DS717F2
QSM
128
192
256
0
64
96

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