CS42888-CQZ Cirrus Logic Inc, CS42888-CQZ Datasheet - Page 18

IC,Soundcard Circuits,CMOS,QFP,64PIN,PLASTIC

CS42888-CQZ

Manufacturer Part Number
CS42888-CQZ
Description
IC,Soundcard Circuits,CMOS,QFP,64PIN,PLASTIC
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet

Specifications of CS42888-CQZ

Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
4 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
105 / 108 (Differential), 102 / 105 (Single-Ended)
Voltage - Supply, Analog
3.14 V ~ 5.25 V
Voltage - Supply, Digital
3.14 V ~ 5.25 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
No. Of Adcs
2
No. Of Dacs
4
No. Of Input Channels
8
No. Of Output Channels
4
Adc / Dac Resolution
24bit
Ic Interface Type
Serial
Supply Voltage Range
3.14V To 5.25V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1183

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS42888-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS42888-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
18
SWITCHING SPECIFICATIONS - ADC/DAC PORT
(Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT C
Figure 4. Serial Audio Interface Slave Mode Timing
Slave Mode
RST pin Low Pulse Width
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate (LRCK)
LRCK Duty Cycle
SCLK Duty Cycle
SCLK High Time
SCLK Low Time
LRCK Rising Edge to SCLK Rising Edge
SCLK Rising Edge to LRCK Falling Edge
SCLK Falling Edge to ADC_SDOUT Output Valid
DAC_SDIN Setup Time Before SCLK Rising Edge
DAC_SDIN Hold Time After SCLK Rising Edge
DAC_SDIN Hold Time After SCLK Rising Edge
ADC_SDOUT Hold Time After SCLK Rising Edge
ADC_SDOUT Valid Before SCLK Rising Edge
Master Mode
Output Sample Rate (LRCK)
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SCLK Rising Edge
SCLK Falling Edge to ADC_SDOUT Output Valid
DAC_SDIN Setup Time Before SCLK Rising Edge
DAC_SDIN Hold Time After SCLK Rising Edge
DAC_SDINx
ADC_SDOUTx
LRCK
SCLK
t
dpd
Parameters
t
lcks
t
ds
t
sckh
t
MSB
MSB
dh
Double-Speed Mode
(Note 21)
Quad-Speed Mode
t
sckl
MSB-1
MSB-1
Single-Speed Mode
All Speed Modes
ADC_SDOUT1
(Note 17)
(Note 18)
(Note 19)
(Note 20)
DAC_SDIN1
LOAD
LRCK
SCLK
(input)
(input)
Figure 5. TDM Serial Audio Interface Timing
= 15 pF.)
Symbol
t
t
t
t
fss
t
t
t
t
t
t
t
sckh
t
t
dval
sckl
lcks
dpd
t
t
dh1
dh2
lcks
dpd
t
dh1
F
F
F
F
fss
fsh
ds
dh
ds
s
s
s
s
0.512
Min
100
t
MSB
fsh
45
50
45
45
16
10
15
45
45
1
4
8
8
5
3
5
5
3
5
-
-
-
-
-
t
ds
t
dh2
MCLK / 256
t
sckh
MSB
64 x Fs
t
dh1
Max
100
200
50
55
50
55
55
35
55
55
35
5
-
-
-
-
-
-
-
-
-
-
-
-
t
MSB-1
dval
t
sckl
CS42888
DS717F2
MSB-1
Units
MHz
MHz
kHz
kHz
kHz
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
%
%

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