AD9220ARS Analog Devices Inc, AD9220ARS Datasheet - Page 20

• Manufacturer Part Number: AD9220ARS
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD9220ARS

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 12 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• No. Of Channels: 2
• Interface Type: Parallel
• Package / Case: 28-SSOP
• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Sampling Rate (per Second): 10M
• Data Interface: Parallel
• Number Of Converters: 7
• Power Dissipation (max): 310mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Number Of Elements: 1
• Resolution: 12Bit
• Architecture: Pipelined
• Sample Rate: 10MSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: ±1/±2.5V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 310mW
• Differential Linearity Error: ±0.75LSB
• Integral Nonlinearity Error: ±1.25LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: AD9220-EB - BOARD EVAL FOR AD9220
• Lead Free Status / Rohs Status: Not Compliant

AD9221/AD9223/AD9220
The AD9221/AD9223/AD9220 contains an internal reference
buffer, A2 (see Figure 9), that simplifies the drive requirements
of an external reference. The external reference must be able to
drive a ≈5 kΩ (± 20%) load. Note that the bandwidth of the
reference buffer is deliberately left small to minimize the refer-
ence noise contribution. As a result, it is not possible to change
the reference voltage rapidly in this mode without the removal
of the CAPT/CAPB Decoupling Network.
Variable Input Span with V
Figure 24 shows an example of the AD9221/AD9223/AD9220
configured for an input span of 2 × VREF centered at 2.5 V. An
external 2.5 V reference drives the VINB pin, thus setting the
common-mode voltage at 2.5 V. The input span can be inde-
pendently set by a voltage divider consisting of R1 and R2,
which generates the VREF signal. A1 buffers this resistor net-
work and drives VREF. Choose this op amp based on accuracy
requirements. It is essential that a minimum of a 10 µF capaci-
tor in parallel with a 0.1 µF low inductance ceramic capacitor
decouple the reference output to ground.
Single-Ended Input with 0 to 2
Figure 25 shows an example of an external reference driving
both VINB and VREF. In this case, both the common-mode
voltage and input span are directly dependent on the value of
VREF. More specifically, the common-mode voltage is equal to
VREF while the input span is equal to 2 × VREF. Thus, the
valid input range extends from 0 to 2 × VREF. For example, if
the REF-191, a 2.048 external reference was selected, the valid
input range extends from 0 to 4.096 V. In this case, 1 LSB of
the AD9221/AD9223/AD9220 corresponds to 1 mV. It is essen-
tial that a minimum of a 10 µF capacitor in parallel with a 0.1 µF
low inductance ceramic capacitor decouple the reference output
to ground.
Low Cost/Power Reference
The external reference circuit shown in Figure 26 uses a low
cost 1.225 V external reference (e.g., AD580 or AD1580) along
with an op amp and transistor. The 2N2222 transistor acts in
+5V
2.5V+VREF
2.5V–VREF
0.1 F
+5V
Figure 24. External Reference—V
on VINB, Resistor Divider to Make VREF)
0.1 F
2.5V
Figure 25. Input Range = 0 V to 2 × VREF
2.5V
REF
2 REF
VREF
0V
0.1 F
22 F
10 F
CM
R1
R2
= 2.5 V
0.1 F
0.1 F
+5V
VREF Range
A1
0.1 F
+5V
CM
VINA
VINB
VREF
SENSE
= 2.5 V (2.5 V
VINA
VINB
VREF
SENSE
AD9221/
AD9223/
AD9220
AD9221/
AD9223/
AD9220
–20–
conjunction with 1/2 of an OP282 to provide a very low imped-
ance drive for VINB. The selected op amp need not be a high
speed op amp and may be selected based on cost, power, and
accuracy.
DIGITAL INPUTS AND OUTPUTS
Digital Outputs
The AD9221/AD9223/AD9220 output data is presented in
positive true straight binary for all input ranges. Table IV indi-
cates the output data formats for various input ranges regardless
of the selected input range. A twos complement output data
format can be created by inverting the MSB.
Input (V)
VINA –VINB
VINA –VINB
VINA –VINB
VINA –VINB
VINA –VINB
Out Of Range (OTR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the converter. OTR is a digital
output that is updated along with the data output corresponding
to the particular sampled analog input voltage. Thus, OTR has
the same pipeline delay (latency) as the digital data. It is LOW
when the analog input voltage is within the analog input range.
It is HIGH when the analog input voltage exceeds the input
range as shown in Figure 27. OTR will remain HIGH until the
analog input returns within the input range and another conver-
sion is completed. By logical ANDing OTR with the MSB and
its complement, overrange high or underrange low conditions
5V
7.5k
Figure 26. External Reference Using the AD1580
and Low Impedance Buffer
1k
OTR DATA OUTPUTS
1
0
0
0
0
1
AD1580
1111 1111 1111
1111 1111 1111
1111 1111 1110
0000 0000 0001
0000 0000 0000
0000 0000 0000
OP282
1k
1/2
3.75V
1.25V
Figure 27. Output Data Format
Table IV. Output Data Format
Condition (V)
= 0
≥ + VREF
< – VREF
= – VREF
= + VREF – 1 LSB 1111 1111 1111
5V
0.1 F
1k
820
OTR
10 F
316
–FS –1/2 LSB
–FS+1/2 LSB
2N2222
–FS
0.1 F
Digital Output
0000 0000 0000
0000 0000 0000
1000 0000 0000
1111 1111 1111
10 F
5V
1.225V
+FS –1 1/2 LSB
0.1 F
+FS –1/2 LSB
+FS
VINA
VINB
VREF
SENSE
AD9221/
AD9223/
AD9220
REV. E
OTR
1
0
0
0
1