AD9220ARS Analog Devices Inc, AD9220ARS Datasheet - Page 15

• Manufacturer Part Number: AD9220ARS
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD9220ARS

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 12 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• No. Of Channels: 2
• Interface Type: Parallel
• Package / Case: 28-SSOP
• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Sampling Rate (per Second): 10M
• Data Interface: Parallel
• Number Of Converters: 7
• Power Dissipation (max): 310mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Number Of Elements: 1
• Resolution: 12Bit
• Architecture: Pipelined
• Sample Rate: 10MSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: ±1/±2.5V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 310mW
• Differential Linearity Error: ±0.75LSB
• Integral Nonlinearity Error: ±1.25LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: AD9220-EB - BOARD EVAL FOR AD9220
• Lead Free Status / Rohs Status: Not Compliant

SINGLE-ENDED MODE OF OPERATION
The AD9221/AD9223/AD9220 can be configured for single-
ended operation using dc or ac coupling. In either case, the
input of the A/D must be driven from an operational amplifier
that will not degrade the A/D’s performance. Because the A/D
operates from a single-supply, it will be necessary to level-shift
ground-based bipolar signals to comply with its input require-
ments. Both dc and ac coupling provide this necessary function,
but each method results in different interface issues that may
influence the system design and performance.
DC COUPLING AND INTERFACE ISSUES
Many applications require the analog input signal to be dc-
coupled to the AD9221/AD9223/AD9220. An operational
amplifier can be configured to rescale and level shift the input
signal so that it is compatible with the selected input range of
the A/D. The input range to the A/D should be selected on the
basis of system performance objectives as well as the analog
power supply availability since this will place certain constraints
on the op amp selection.
Many of the new high performance op amps are specified for
only ± 5 V operation and have limited input/output swing capa-
bilities. Therefore, the selected input range of the AD9221/
AD9223/AD9220 should be sensitive to the headroom require-
ments of the particular op amp to prevent clipping of the signal.
Also, since the output of a dual supply amplifier can swing
below –0.3 V, clamping its output should be considered in some
applications.
In some applications, it may be advantageous to use an op
amp specified for single-supply 5 V operation since it will
inherently limit its output swing to within the power supply
rails. An amplifier like the AD8041, AD8011, and AD817 are
useful for this purpose. Rail-to-rail output amplifiers such as
the AD8041 allow the AD9221/AD9223/AD9220 to be con-
figured for larger input spans, which improves the noise
performance.
If the application requires the largest input span (i.e., 0 V to
5 V) of the AD9221/AD9223/AD9220, the op amp will require
larger supplies to drive it. Various high speed amplifiers in the
Op Amp Selection Guide of this data sheet can be selected to
accommodate a wide range of supply options. Once again,
clamping the output of the amplifier should be considered for
these applications.
Two dc-coupled op amp circuits using a noninverting and
inverting topology are discussed below. Although not shown,
the noninverting and inverting topologies can be easily config-
ured as part of an antialiasing filter by using a Sallen-Key or
Multiple-Feedback topology, respectively. An additional R-C
REV. E
V
V
CC
EE
Figure 12. Simple Clamping Circuit
OPTIONAL
AC COUPLING
CAPACITOR
30
R
S1
AVDD
D2
1N4148
D1
1N4148
20
R
S2
AD9221/
AD9223/
AD9220
–15–
network can be inserted between the op amp’s output and the
AD9221/AD9223/AD9220 input to provide a real pole.
Simple Op Amp Buffer
In the simplest case, the input signal to the AD9221/AD9223/
AD9220 will already be biased at levels in accordance with the
selected input range. It is simply necessary to provide an
adequately low source impedance for the VINA and VINB
analog input pins of the A/D. Figure 13 shows the recommended
configuration for a single-ended drive using an op amp. In this
case, the op amp is shown in a noninverting unity gain configu-
ration driving the VINA pin. The internal reference drives the
VINB pin. Note that the addition of a small series resistor of
30 Ω to 50 Ω connected to VINA and VINB will be beneficial
in nearly all cases. Refer to the Analog Input Operation section
for a discussion on resistor selection. Figure 13 shows the
proper connection for a 0 V to 5 V input range. Alternative
single-ended input ranges of 0 V to 2 × VREF can also be real-
ized with the proper configuration of VREF (refer to the Using
the Internal Reference section).
Op Amp with DC Level Shifting
Figure 14 shows a dc-coupled level shifting circuit employing an
op amp, A1, to sum the input signal with the desired dc offset.
Configuring the op amp in the inverting mode with the given
resistor values results in an ac signal gain of –1. If the signal
inversion is undesirable, interchange the VINA and VINB con-
nections to re-establish the original signal polarity. The dc voltage
at VREF sets the common-mode voltage of the AD9221/AD9223/
AD9220. For example, when VREF = 2.5 V, the output level
from the op amp will also be centered around 2.5 V. The use of
ratio matched, thin-film resistor networks will minimize gain
and offset errors. Also, an optional pull-up resistor, R
used to reduce the output load on VREF to ± 1 mA.
–VREF
+VREF
AVDD
VREF
5V
0V
NOTES
1
2
Figure 13. Single-Ended AD9221/AD9223/AD9220
Op Amp Drive Circuit
Figure 14. Single-Ended Input with DC-Coupled
Level Shift
OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D
OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE
R
P
2
0V
0.1 F
500
DC
+V
U1
–V
1
AD9221/AD9223/AD9220
500
500
1
1
3
2
10 F
2.5V
A1
+V
R
7
4
S
CC
0.1 F
NC
NC
500
1
5
0.1 F
6
1
R
S
R
R
S
S
VINA
VINB
VREF
SENSE
VINA
VINB
AD9221/
AD9223/
AD9220
AD9221/
AD9223/
AD9220
P
, may be