PIC18LF4221-I/ML Microchip Technology, PIC18LF4221-I/ML Datasheet - Page 58

• Manufacturer Part Number: PIC18LF4221-I/ML
• Description: 4 KB Flash, 512 RAM 44 QFN 8x8x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4221-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2221/2321/4221/4321 FAMILY
TABLE 5-4:
DS39689F-page 58
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE
TRISD
TRISC
TRISB
TRISA
LATE
LATD
LATC
LATB
LATA
PORTE
PORTD
PORTC
PORTB
PORTA
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1:
Register
(5)
2:
3:
4:
5:
(5)
(5)
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 5-3 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
2221 2321 4221 4321
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INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Brown-out Reset
Power-on Reset,
11-1 1111
00-0 0000
00-0 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
00-0 0000
0000 -111
1111 1111
1111 1111
1111 1111
1111 1111
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- xxxx
---- x---
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000
(5)
(5)
(5)
RESET Instruction,
11-1 1111
00-0 0000
00-0 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
00-0 0000
0000 -111
1111 1111
1111 1111
1111 1111
1111 1111
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
---- u---
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu0u 0000
MCLR Resets,
Stack Resets
WDT Reset,
(5)
(5)
(5)
© 2009 Microchip Technology Inc.
Wake-up via WDT
uu-u uuuu
uu-u uuuu
uu-u uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
-uuu uuuu
uu-u uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
---- u---
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
or Interrupt
(1)
(1)
(1)
(5)
(5)
(5)