PIC18LF4221-I/ML Microchip Technology, PIC18LF4221-I/ML Datasheet - Page 236

4 KB Flash, 512 RAM 44 QFN 8x8x0.9mm TUBE

PIC18LF4221-I/ML

Manufacturer Part Number
PIC18LF4221-I/ML
Description
4 KB Flash, 512 RAM 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF4221-I/ML

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC18F2221/2321/4221/4321 FAMILY
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(V
V
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 20-1:
DS39689F-page 236
REF
DD
+ and RA2/AN2/V
and V
Note 1:
SS
2:
), or the voltage level on the RA3/AN3/
Converter
10-Bit
Channels AN5 through AN7 are not available on 28-pin devices.
I/O pins have diode protection to V
A/D
Reference
Voltage
A/D BLOCK DIAGRAM
REF
-/CV
REF
pins.
V
V
REF
REF
+
-
(Input Voltage)
VCFG<1:0>
V
AIN
DD
and V
X
X
1
0
0
1
X
X
V
SS
DD
complete,
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input, or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is
ADRESH:ADRESL register pair, the GO/DONE bit
(ADCON0 register) is cleared and A/D Interrupt Flag bit,
ADIF, is set. The block diagram of the A/D module is
shown in Figure 20-1.
.
V
SS
CHS<3:0>
the
result
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
© 2009 Microchip Technology Inc.
is
loaded
AN12
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
into
(1)
(1)
(1)
the

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