PIC18LF4221-I/ML Microchip Technology, PIC18LF4221-I/ML Datasheet - Page 125

• Manufacturer Part Number: PIC18LF4221-I/ML
• Description: 4 KB Flash, 512 RAM 44 QFN 8x8x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4221-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 11-9:
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
© 2009 Microchip Technology Inc.
PORTE
LATE
TRISE
ADCON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1:
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
MCLR/V
Legend:
Note 1:
Name
(2)
2:
2:
Pin
PP
/RE3
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin devices.
RE3 does not have a corresponding TRIS bit to control data direction.
(1)
Bit 7
IBF
—
—
—
PORTE I/O SUMMARY
Function
MCLR
RE0
AN5
RE1
AN6
RE2
AN7
RE3
WR
V
RD
CS
PIC18F2221/2321/4221/4321 FAMILY
PP
Bit 6
OBF
—
—
—
Setting
TRIS
—
—
—
0
1
1
1
0
1
1
1
0
1
1
1
(2)
VCFG1
IBOV
Bit 5
I/O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
—
—
Type
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
I/O
ST
ST
ST
ST
ST
PSPMODE
VCFG0
Bit 4
—
—
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
PSP read enable input (PSP enabled).
A/D Input Channel 5; default input configuration on POR.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
A/D Input Channel 6; default input configuration on POR.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
A/D Input Channel 7; default input configuration on POR.
External Master Clear input; enabled when MCLRE Configuration bit
is set.
High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
RE3
PCFG3
Bit 3
—
—
(1,2)
PORTE Data Latch Register
(Read and Write to Data Latch)
TRISE2
PCFG2
Bit 2
RE2
Description
TRISE1
PCFG1
Bit 1
RE1
TRISE0
PCFG0
Bit 0
DS39689F-page 125
RE0
on page
Values
Reset
58
58
58
57