LTC3675EUFF#PBF Linear Technology, LTC3675EUFF#PBF Datasheet - Page 21

• Manufacturer Part Number: LTC3675EUFF#PBF
• Description: IC, PMIC, 1A, QFN-44
• Manufacturer: Linear Technology

Specifications of LTC3675EUFF#PBF

• Supply Voltage: 5.5V
• No. Of Step-down Dc - Dc Converters: 4
• No. Of Ldo Regulators: 1
• Digital Ic Case Style: QFN
• No. Of Pins: 44
• No. Of Regulated Outputs: 7
• Operating Temperature Range: -40°C To +125°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OPERATION
POWER-UP AND POWER-DOWN VIA ENABLE PIN OR I
With the LTC3675 in its off state, a regulator can be enabled
either via its enable pin or I
is enabled via its enable pin at time t
HIGH for 5 seconds and at t
regulator stays enabled until time t
command is issued via I
down and stays off for 1 second. At time t
exits from the power down state. Since the buck regula-
tor 1 is still enabled via its enable pin, it powers back up.
WAKE also gets pulled HIGH for 5 seconds. The RSTB
pin gets pulled HIGH 200ms after the buck regulator 1 is
in its PGOOD state.
LED CURRENT PROGRAMMING
The LED current is primarily controlled through the LED
DAC register at I
an 8 bit current DAC. A 20k resistor placed between the
LED_FS pin and ground provides a current reference for the
DAC which results in 98μA of programmed LED current per
LSB. For example, programming a LED DAC register code
of 64h will result in a LED current of 9.8mA and a full-scale
setting of FFh will result in a LED current of 25mA.
ister at sub-address 7 effectively doubles the programmed
LED current. With a 20k resistor from LED_FS to ground
each LSB will be 196μA. Programming a LED DAC register
SDA
SCL
The 2xFS bit which is bit 3 of the LED confi guration reg-
START
0
0
1
0
0
2
SDA
SCL
t
HD, STA
2
0
0
3
C sub-address 8. This register controls
CONDITION
ADDRESS
START
1
1
4
0
0
5
2
2
C. In Figure 2c, buck regulator 1
C. The buck regulator powers
t
LOW
0
0
6
2
t
r
is pulled LOW. The buck
1
1
7
t
HIGH
t
SU, DAT
WR
1
0
0
8
3
. The WAKE pin goes
t
f
when a hard reset
ACK
9
4
A7
, the LTC3675
1
t
HD, DAT
A6
2
Figure 3. I
A5
3
DATA BYTE A
A4
2
4
C
REPEATED START
2
C Bus Operation
CONDITION
A3
5
code of 64h will result in a LED current of 19.6mA and
a full-scale setting of FFh will result in an LED current of
50mA. The 2xFS mode is only intended for use when the
output voltage is below 20V.
I
The LTC3675 may communicate with a bus master using
the standard I
(Figure 2) shows the relationship of the signals on the
bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 SMBus accelerator,
are required on these lines. The LTC3675 is both a slave
receiver and slave transmitter. The I
SDA and SCL are scaled internally to the DV
DV
the bus pull-up resistors.
The I
When DV
LTC3675 registers are set to their default confi gurations.
I
The I
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I
device. It also contains input fi lters designed to suppress
glitches should the bus become corrupted.
2
2
A2
6
C INTERFACE
C Bus Speed
t
SU, STA
CC
A1
2
7
2
C port has an undervoltage lockout on the DV
should be connected to the same power supply as
C port is designed to be operated at speeds of up
t
HD, STA
t
A0
SP
8
CC
is below 1V, the I
ACK
9
2
C 2-wire interface. The timing diagram
B7
1
B6
2
CONDITION
B5
3
STOP
DATA BYTE B
2
B4
4
C serial port is cleared and the
t
SU, STO
t
BUF
B3
5
CONDITION
START
B2
6
2
C compliant master
3675 F03
2
C control signals,
B1
7
LTC3675
B0
8
ACK
CC
9
21
supply.
CC
STOP
pin.
3675f