PIC18F46K20-E/P Microchip Technology, PIC18F46K20-E/P Datasheet - Page 363

• Manufacturer Part Number: PIC18F46K20-E/P
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, DIP-40
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K20-E/P

• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3936Byte
• Cpu Speed: 64MHz
• No. Of Timers: 4
• Core Size: 8 Bit
• Program Memory Size: 32768 Words
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: CCP, ECCP, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 14 Channel
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20
• Lead Free Status / Rohs Status: Details

ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
OFST
FSR2
Contents
of 0A2Ch
W
Contents
of 0A2Ch
Q1
ADD W to Indexed
(Indexed Literal Offset mode)
ADDWF
0  k  95
d  [0,1]
(W) + ((FSR2) + k)  dest
N, OV, C, DC, Z
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’ (default).
1
1
ADDWF
Read ‘k’
0010
Q2
=
=
=
=
=
=
[OFST] , 0
[k] {,d}
01d0
17h
2Ch
0A00h
20h
37h
20h
Process
Data
Q3
kkkk
destination
Write to
Q4
kkkk
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
PIC18F2XK20/4XK20
Q Cycle Activity:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
Decode
FLAG_OFST
FSR2
Contents
of 0A0Ah
Contents
of 0A0Ah
OFST
FSR2
Contents
of 0A2Ch
Contents
of 0A2Ch
Q1
Q1
register ‘f’
BSF
Bit Set Indexed
(Indexed Literal Offset mode)
BSF [k], b
0  f  95
0  b  7
1  ((FSR2) + k)<b>
None
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
1
1
Set Indexed
(Indexed Literal Offset mode)
SETF [k]
0  k  95
FFh  ((FSR2) + k)
None
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
1
1
SETF
Read ‘k’
Read
1000
0110
Q2
Q2
=
=
=
=
=
=
=
=
2Ch
0A00h
00h
FFh
[FLAG_OFST], 7
[OFST]
bbb0
1000
0Ah
0A00h
55h
D5h
Process
Process
Data
Data
Q3
Q3
DS41303G-page 363
kkkk
kkkk
destination
Write to
register
Write
Q4
Q4
kkkk
kkkk