MAX1441GUP/V+ Maxim Integrated Products, MAX1441GUP/V+ Datasheet - Page 28

• Manufacturer Part Number: MAX1441GUP/V+
• Description: Touch Screen Converters & Controllers PROXIMITY SENSR el Proximity and Tou
• Manufacturer: Maxim Integrated Products

Specifications of MAX1441GUP/V+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Automotive, Two-Channel Proximity and
Touch Sensor
Table 11. Special-Function Register Bit Description (continued)
28
WU1.1–RE1
WU1.2–AO1
WU1[7:3]
WU2 (05h, 01h)
Initialization
Read/Write Access
WU2.0–AE2
WU2.1–RE2
WU2.2–AO2
WU2[7:3]
FEL (06h, 01h)
Initialization
Read/Write Access
FEL[5:0]
FEL[7:6]
FEB (07h, 01h)
Initialization
Read/Write Access
FEB[4:0]
FEB[7:5]
CRSLT1L (08h, 01h)
Initialization
Read/Write Access
CRSLT1L.0–OVR1
CRSLT1L[3:1]
CRSLT1L[7:4]
REGISTER
CH1 Rate-of-Change Wake-Up Threshold Enable. Setting this bit to 1 enables the rate-of-change
wake-up threshold detection. Clearing this bit to 0 disables the rate-of-change wake-up threshold
detection.
CH1 AND/OR Mode Enable. Setting this bit to 1 causes an interrupt to the CPU when both the absolute
and rate-of-change threshold are exceeded. Both AEI and REI must be enabled when AO1 is set to 1.
Clearing this bit to 0 causes an interrupt to the CPU when either the absolute threshold or rate-of-change
threshold is exceeded.
Reserved. Read returns 0.
Channel 2 Wake-Up Control Register (8-Bit Register)
This register is cleared to 04h on all forms of reset.
Unrestricted read/write.
CH2 Absolute Wake-Up Threshold Enable. Setting this bit to 1 enables the absolute wake-up
threshold detection. Clearing this bit to 0 disables the absolute wake-up threshold detection.
CH2 Rate-of-Change Wake-Up Threshold Enable. Setting this bit to 1 enables the rate-of-change
wake-up threshold detection. Clearing this bit to 0 disables the rate-of-change wake-up threshold
detection.
CH2 AND/OR Mode Enable. Setting this bit to 1 causes an interrupt to the CPU when both the absolute
and rate-of-change threshold are exceeded. Clearing this bit to 0 causes an interrupt to the CPU when
either the absolute or rate-of-change threshold is exceeded.
Reserved. Read returns 0.
Excitation Frequency Low-Limit Register (8-Bit Register)
This register is set to 1Eh on all forms of reset.
Unrestricted read/write.
Excitation Frequency Low-Limit Bits [5:0]. These bits set the lower end of the excitation frequency
(FEL x 10kHz).
Reserved. Read returns 0.
Excitation Frequency Spread-Spectrum Bandwidth Register (8-Bit Register)
This register is cleared to 00h on all forms of reset.
Unrestricted read/write.
Excitation Frequency Spread-Spectrum Bandwidth Bits [4:0]. These bits set the excitation frequency
bandwidth (FEB x 20kHz).
Reserved. Read returns 0.
Channel 1 Conversion Result Register (8-Bit Register)
This register is cleared to 00h on all forms of reset.
This register is read only.
CH1 Overrange Flag. The overrange flag is set to 1 by hardware if the current conversion causes
overranging of the C–to–D conversion. This bit is cleared to 0 if the current conversion does not cause
overranging.
Reserved. Read returns 0.
Channel 1 Conversion Result Bits [3:0]. This register contains the lower 4 bits of the C–to–D conversion.
DESCRIPTION