ATMEGA32A-MNR Atmel, ATMEGA32A-MNR Datasheet - Page 53

• Manufacturer Part Number: ATMEGA32A-MNR
• Description: IC MCU AVR 32K 16MHZ 44VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8155C–AVR–02/11
Figure 12-3. Synchronization when Reading an Externally Applied Pin Value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As
indicated by the two arrows t
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
the clock. In this case, the delay t
Figure 12-4. Synchronization when Reading a Software Assigned Pin Value
INSTRUCTIONS
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
SYSTEM CLK
SYNC LATCH
Figure
PINxn
PINxn
12-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of
r16
r17
r17
out PORTx, r16
pd,max
XXX
pd
and t
through the synchronizer is one system clock period.
pd,min
t
pd, max
, a single signal transition on the pin will be delayed
0x00
0x00
nop
XXX
t
pd
t
0xFF
pd, min
in r17, PINx
in r17, PINx
ATmega32A
0xFF
0xFF
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