ATMEGA32A-MNR Atmel, ATMEGA32A-MNR Datasheet - Page 43

• Manufacturer Part Number: ATMEGA32A-MNR
• Description: IC MCU AVR 32K 16MHZ 44VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.5.2
8155C–AVR–02/11
WDTCR – Watchdog Timer Control Register
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then reset
the MCUCSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the Reset Flags.
• Bits 7:5 – Reserved Bits
These bits are reserved bits in the ATmega32A and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE
bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
• Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
Bit
Read/Write
Initial Value
1. In the same operation, write a logic one to WDTOE and WDE. A logic one must be writ-
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
ten to WDE even though it is set to one before the disable operation starts.
R
7
–
0
R
6
–
0
R
5
–
0
WDTOE
R/W
4
0
WDE
R/W
3
0
WDP2
R/W
2
0
WDP1
R/W
1
0
ATmega32A
WDP0
R/W
0
0
WDTCR
43