ATMEGA32A-MNR Atmel, ATMEGA32A-MNR Datasheet - Page 117
![IC MCU AVR 32K 16MHZ 44VQFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA32A-MNR
Manufacturer Part Number
ATMEGA32A-MNR
Description
IC MCU AVR 32K 16MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA32A-MU.pdf
(353 pages)
Specifications of ATMEGA32A-MNR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.10.7
16.10.8
8155C–AVR–02/11
TIMSK – Timer/Counter Interrupt Mask Register
TIFR – Timer/Counter Interrupt Flag Register
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the analog comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
Note:
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture Interrupt is enabled. The corresponding Interrupt
Vector
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding
Interrupt Vector
TIFR, is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding
Interrupt Vector
TIFR, is set.
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page
Note:
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See “Interrupts” on page
1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are
1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described
See “Accessing 16-bit Registers” on page 94.
described in this section. The remaining bits are described in their respective timer sections.
in this section. The remaining bits are described in their respective timer sections.
OCIE2
OCF2
R/W
R/W
(See “Interrupts” on page
(See “Interrupts” on page
7
0
7
0
TOIE2
TOV2
R/W
R/W
45.) is executed when the TOV1 Flag, located in TIFR, is set.
6
0
6
0
45.) is executed when the ICF1 Flag, located in TIFR, is set.
TICIE1
R/W
ICF1
R/W
(1)
5
0
5
0
OCIE1A
OCF1A
R/W
R/W
45.) is executed when the OCF1A Flag, located in
45.) is executed when the OCF1B Flag, located in
4
0
4
0
OCIE1B
OCF1B
R/W
R/W
3
0
3
0
TOIE1
TOV1
R/W
R/W
2
0
2
0
OCIE0
OCF0
R/W
R/W
1
0
1
0
ATmega32A
TOIE0
TOV0
R/W
R/W
0
0
0
0
TIMSK
TIFR
117
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