PIC32MX575F512H-80I/PT Microchip Technology, PIC32MX575F512H-80I/PT Datasheet - Page 66

• Manufacturer Part Number: PIC32MX575F512H-80I/PT
• Description: IC MCU 32BIT 512KB FLASH 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512H-80I/PT

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC32
• No. Of I/o's: 53
• Ram Memory Size: 64KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Digital Ic Case Style: TQFP
• Embedded Interface Type: CAN, I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 4-11:
Legend:
Note
5220 I2C3AADD
5230 I2C3AMSK
5240 I2C3ABRG
5250 I2C3ATRN
5260 I2C3ARCV
5300
5310
5320
5330
5340
5350
5360
1:
I2C1CON
I2C1STAT
I2C1MSK
I2C1BRG
I2C1ADD
I2C1TRN
I2C1RCV
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
I2C1, I2C1A, I2C2A, AND I2C3A REGISTER MAP
ACKSTAT
31/15
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRSTAT
30/14
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCLREL
28/12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STRICT
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
A10M
BCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GCSTAT
DISSLW
(1)
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(CONTINUED)
ADD10
SMEN
24/8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits
IWCOL
GCEN
23/7
—
—
—
—
—
—
—
—
—
—
—
—
STREN
I2COV
22/6
I2C1BRG<11:0>
I2C1BRG<11:0>
—
—
—
—
—
—
—
—
—
—
—
—
ACKDT
21/5
D/A
—
—
—
—
—
—
—
—
—
—
—
—
ADD<9:0>
MSK<9:0>
ADD<9:0>
MSK<9:0>
ACKEN
I2CR1DATA<7:0>
I2CR1DATA<7:0>
I2CT1DATA<7:0>
I2CT1DATA<7:0>
20/4
—
—
—
—
—
—
—
—
—
—
—
—
P
RCEN
19/3
—
—
—
—
—
—
—
—
—
—
—
—
S
18/2
PEN
R/W
—
—
—
—
—
—
—
—
—
—
—
—
RSEN
17/1
RBF
—
—
—
—
—
—
—
—
—
—
—
—
16/0
SEN
TBF
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000