PIC32MX575F512H-80I/PT Microchip Technology, PIC32MX575F512H-80I/PT Datasheet - Page 45

• Manufacturer Part Number: PIC32MX575F512H-80I/PT
• Description: IC MCU 32BIT 512KB FLASH 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512H-80I/PT

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC32
• No. Of I/o's: 53
• Ram Memory Size: 64KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Digital Ic Case Style: TQFP
• Embedded Interface Type: CAN, I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

4.0
PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB
of unified virtual memory address space. All memory
regions, including program, data memory, SFRs, and
Configuration registers, reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX5XX/6XX/7XX
devices to execute from data memory.
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
• Simple memory mapping with Fixed Mapping
• Cacheable (KSEG0) and non-cacheable (KSEG1)
 2009 Microchip Technology Inc.
Note:
(KSEG0/KSEG1) mode address space
program space
runaway code
Translation (FMT) unit
address regions
MEMORY ORGANIZATION
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a compre-
hensive reference source. For detailed
information, refer to Section 3. “Memory
Organization”
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
(DS61115)
in
the
Preliminary
PIC32MX5XX/6XX/7XX
4.1
PIC32MX5XX/6XX/7XX microcontrollers implement
two address schemes: virtual and physical. All hard-
ware resources such as program memory, data mem-
ory and peripherals are located at their respective
physical addresses. Virtual addresses are exclusively
used by the CPU to fetch and execute instructions as
well as access peripherals. Physical addresses are
used by bus master peripherals such as DMA and
Flash controller that access memory independently of
CPU.
The memory maps for the PIC32MX5XX/6XX/7XX
devices are shown in Figure 4-1, Figure 4-2, and
Figure 4-3.
4.1.1
Table 4-1 through Table 4-44 contain the peripheral
address maps for the PIC32MX5XX/6XX/7XX devices.
Peripherals located on the PB Bus are mapped to 512
byte boundaries. Peripherals on the FPB Bus are
mapped to 4 Kbyte boundaries.
PIC32MX5XX/6XX/7XX Memory
Layout
PERIPHERAL REGISTERS
LOCATIONS
DS61156B-page 45